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    SubjectRe: [PATCH 1/2] dt-bindings: riscv: sifive-l2: add a PolarFire SoC compatible
    On Thu, 25 Aug 2022 19:04:17 +0100, Conor Dooley wrote:
    > From: Conor Dooley <conor.dooley@microchip.com>
    >
    > The l2 cache on PolarFire SoC is cross between that of the fu540 and
    > the fu740. It has the extra interrupt from the fu740 but the lower
    > number of cache-sets. Add a specific compatible to avoid the likes
    > of:
    >
    > mpfs-polarberry.dtb: cache-controller@2010000: interrupts: [[1], [3], [4], [2]] is too long
    >
    > Fixes: 34fc9cc3aebe ("riscv: dts: microchip: correct L2 cache interrupts")
    > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
    > ---
    > .../bindings/riscv/sifive-l2-cache.yaml | 79 ++++++++++++-------
    > 1 file changed, 49 insertions(+), 30 deletions(-)
    >

    Reviewed-by: Rob Herring <robh@kernel.org>

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