Messages in this thread | | | Date | Tue, 30 Aug 2022 13:00:28 -0500 | From | Rob Herring <> | Subject | Re: [PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC support |
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On Mon, Aug 22, 2022 at 10:19:45PM +0300, Serge Semin wrote: > Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a > with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There > are individual IRQs for each ECC and DFI events.The dedicated scrubber > clock source is absent since it's fully synchronous to the core clock. > In addition to that the DFI-DDR PHY CSRs can be accessed via a separate > registers space.
Are you sure the phy and dfi irq shouldn't be a separate device?
Rob
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