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    Subject[PATCH AUTOSEL 5.19 32/33] drm/amdgpu: add sdma instance check for gfx11 CGCG
    Date
    From: Tim Huang <tim.huang@amd.com>

    [ Upstream commit 00047c3d967d7ef8adf8bac3c3579294a3bc0bb1 ]

    For some ASICs, like GFX IP v11.0.1, only have one SDMA instance,
    so not need to configure SDMA1_RLC_CGCG_CTRL for this case.

    Signed-off-by: Tim Huang <tim.huang@amd.com>
    Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
    Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 18 ++++++++++++------
    1 file changed, 12 insertions(+), 6 deletions(-)

    diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
    index a4a6751b1e449..30998ac47707c 100644
    --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
    +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
    @@ -5090,9 +5090,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
    data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
    WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);

    - data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
    - data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
    - WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
    + /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
    + if (adev->sdma.num_instances > 1) {
    + data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
    + data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
    + WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
    + }
    } else {
    /* Program RLC_CGCG_CGLS_CTRL */
    def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
    @@ -5121,9 +5124,12 @@ static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *ade
    data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
    WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);

    - data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
    - data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
    - WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
    + /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
    + if (adev->sdma.num_instances > 1) {
    + data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
    + data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
    + WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
    + }
    }
    }

    --
    2.35.1
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