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SubjectRe: [PATCH v5 4/7] reset: imx7: Fix the iMX8MP PCIe PHY PERST support
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Hi,

On Di, 2022-08-30 at 15:46 +0800, Richard Zhu wrote:
> On i.MX7/iMX8MM/iMX8MQ, the initialized default value of PERST bit(BIT3)
> of SRC_PCIEPHY_RCR is 1b'1.
> But i.MX8MP has one inversed default value 1b'0 of PERST bit.
>
> And the PERST bit should be kept 1b'1 after power and clocks are stable.
> So fix the i.MX8MP PCIe PHY PERST support here.
>
> Fixes: e08672c03981 ("reset: imx7: Add support for i.MX8MP SoC")
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
> Tested-by: Marek Vasut <marex@denx.de>
> Tested-by: Richard Leitner <richard.leitner@skidata.com>
> Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>

I've applied this patch to the reset/fixes branch.

regards
Philipp

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