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    Subject[PATCH 5.19 102/158] perf/x86/intel: Fix pebs event constraints for ADL
    Date
    From: Kan Liang <kan.liang@linux.intel.com>

    commit cde643ff75bc20c538dfae787ca3b587bab16b50 upstream.

    According to the latest event list, the LOAD_LATENCY PEBS event only
    works on the GP counter 0 and 1 for ADL and RPL.

    Update the pebs event constraints table.

    Fixes: f83d2f91d259 ("perf/x86/intel: Add Alder Lake Hybrid support")
    Reported-by: Ammy Yi <ammy.yi@intel.com>
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: stable@vger.kernel.org
    Link: https://lkml.kernel.org/r/20220818184429.2355857-1-kan.liang@linux.intel.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/x86/events/intel/ds.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/arch/x86/events/intel/ds.c
    +++ b/arch/x86/events/intel/ds.c
    @@ -822,7 +822,7 @@ struct event_constraint intel_glm_pebs_e

    struct event_constraint intel_grt_pebs_event_constraints[] = {
    /* Allow all events as PEBS with no flags */
    - INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0xf),
    + INTEL_HYBRID_LAT_CONSTRAINT(0x5d0, 0x3),
    INTEL_HYBRID_LAT_CONSTRAINT(0x6d0, 0xf),
    EVENT_CONSTRAINT_END
    };

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