Messages in this thread | | | From | "Gupta, Nipun" <> | Subject | RE: [RFC PATCH v2 2/6] bus/cdx: add the cdx bus driver | Date | Mon, 29 Aug 2022 04:49:21 +0000 |
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[AMD Official Use Only - General]
> -----Original Message----- > From: Jason Gunthorpe <jgg@nvidia.com> > Sent: Friday, August 26, 2022 5:38 AM > To: Robin Murphy <robin.murphy@arm.com> > Cc: Saravana Kannan <saravanak@google.com>; Greg KH > <gregkh@linuxfoundation.org>; Gupta, Nipun <Nipun.Gupta@amd.com>; > robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org; rafael@kernel.org; > eric.auger@redhat.com; alex.williamson@redhat.com; cohuck@redhat.com; > Gupta, Puneet (DCG-ENG) <puneet.gupta@amd.com>; > song.bao.hua@hisilicon.com; mchehab+huawei@kernel.org; maz@kernel.org; > f.fainelli@gmail.com; jeffrey.l.hugo@gmail.com; Michael.Srba@seznam.cz; > mani@kernel.org; yishaih@nvidia.com; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; kvm@vger.kernel.org; okaya@kernel.org; Anand, > Harpreet <harpreet.anand@amd.com>; Agarwal, Nikhil > <nikhil.agarwal@amd.com>; Simek, Michal <michal.simek@amd.com>; git > (AMD-Xilinx) <git@amd.com> > Subject: Re: [RFC PATCH v2 2/6] bus/cdx: add the cdx bus driver > > [CAUTION: External Email] > > On Thu, Aug 25, 2022 at 08:57:49PM +0100, Robin Murphy wrote: > > > To my mind, it would definitely help to understand if this is a *real* > > discoverable bus in hardware, i.e. does one have to configure one's device > > with some sort of CDX wrapper at FPGA synthesis time, that then physically > > communicates with some sort of CDX controller to identify itself once > > loaded; or is it "discoverable" in the sense that there's some firmware on > > an MCU controlling what gets loaded into the FPGA, and software can query > > that and get back whatever precompiled DTB fragment came bundled with the > > bitstream, i.e. it's really more like fpga-mgr in a fancy hat? > > So much of the IP that you might want to put in a FPGA needs DT, I > don't thing a simplistic AMBA like discoverable thing would be that > interesting. > > Think about things like FPGA GPIOs being configured as SPI/I2C, then > describing the board config of SPI/I2C busses, setting up PCI bridges, > flash storage controllers and all sorts of other typically embedded > stuff that really relies on DT these days. > > It would be nice if Xilinx could explain more about what environment > this is targetting. Is it Zynq-like stuff?
This solution is not targeted for GPIO/SPI or I2C like devices which rely on DT, but would have PCI like network/storage devices. It is not targeted for Zynq platform. I have added more details on other mail. Please refer to that mail.
Thanks, Nipun
> > Jason
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