Messages in this thread | | | From | Linus Torvalds <> | Date | Thu, 25 Aug 2022 14:54:00 -0700 | Subject | Re: [PATCH] wait_on_bit: add an acquire memory barrier |
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On Thu, Aug 25, 2022 at 2:03 PM Mikulas Patocka <mpatocka@redhat.com> wrote: > > Here I reworked your patch, so that test_bit_acquire is defined just like > test_bit. There's some code duplication (in > include/asm-generic/bitops/generic-non-atomic.h and in > arch/x86/include/asm/bitops.h), but that duplication exists in the > test_bit function too.
This looks fine to me, and I like how you fixed up buffer_uptodate() while at it.
> I tested it on x86-64 and arm64. On x86-64 it generates the "bt" > instruction for variable-bit test and "shr; and $1" for constant bit test.
That shr/and is almost certainly pessimal for small constant values at least, and it's better done as "movq %rax" followed by "test %rax". But I guess it depends on the bit value (and thus the constant size).
Doing a "testb $imm8" would likely be optimal, but you'll never get that with smp_load_acquire() on x86 unless you use inline asm, because of how we're doing it with a volatile pointer.
Anyway, you could try something like this:
static __always_inline bool constant_test_bit(long nr, const volatile unsigned long *addr) { bool oldbit;
asm volatile("testb %2,%1" CC_SET(nz) : CC_OUT(nz) (oldbit) : "m" (((unsigned char *)addr)[nr >> 3]), "Ir" (1 << (nr & 7)) :"memory"); return oldbit; }
for both the regular test_bit() and for the acquire (since all loads are acquires on x86, and using an asm basically forces a memory load so it just does that "volatile" part.
But that's a separate optimization and independent of the acquire thing.
> For me, the kernel 6.0-rc2 doesn't boot in an arm64 virtual machine at all > (with or without this patch), so I only compile-tested it on arm64. I have > to bisect it.
Hmm. I'm running it on real arm64 hardware (rc2+ - not your patch), so I wonder what's up..
Linus
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