Messages in this thread Patch in this message | | | From | Rob Herring <> | Date | Thu, 25 Aug 2022 13:08:00 -0500 | Subject | [PATCH RFC v1 1/3] perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event |
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Arm SPEv1.2 (Armv8.7/v9.2) adds a new event, 'not taken', in bit 6 of the PMSEVFR_EL1 register. Update arm_spe_pmsevfr_res0() to support the additional event.
Signed-off-by: Rob Herring <robh@kernel.org>
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7c71358d44c4..57904c11aece 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -312,6 +312,8 @@ BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0)) #define SYS_PMSEVFR_EL1_RES0_8_3 \ (SYS_PMSEVFR_EL1_RES0_8_2 & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) +#define SYS_PMSEVFR_EL1_RES0_8_7 \ + (SYS_PMSEVFR_EL1_RES0_8_3 & ~BIT_ULL(6)) #define SYS_PMSLATFR_EL1 sys_reg(3, 0, 9, 9, 6) #define SYS_PMSLATFR_EL1_MINLAT_SHIFT 0 @@ -847,6 +849,7 @@ #define ID_AA64DFR0_PMSVER_8_2 0x1 #define ID_AA64DFR0_PMSVER_8_3 0x2 +#define ID_AA64DFR0_PMSVER_8_7 0x3 #define ID_DFR0_PERFMON_SHIFT 24 diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index b65a7d9640e1..a75b03b5c8f9 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -677,9 +677,11 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) case ID_AA64DFR0_PMSVER_8_2: return SYS_PMSEVFR_EL1_RES0_8_2; case ID_AA64DFR0_PMSVER_8_3: + return SYS_PMSEVFR_EL1_RES0_8_3; + case ID_AA64DFR0_PMSVER_8_7: /* Return the highest version we support in default */ default: - return SYS_PMSEVFR_EL1_RES0_8_3; + return SYS_PMSEVFR_EL1_RES0_8_7; } } -- b4 0.10.0-dev
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