Messages in this thread Patch in this message | | | From | Li Yang <> | Subject | [PATCH 04/11] arm64: dts: ls1043a: Add SCFG phandle for PCIe nodes | Date | Wed, 24 Aug 2022 17:36:55 -0500 |
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From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The LS1043A PCIe controller has some control registers in SCFG block, so add the SCFG phandle for each PCIe controller node.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Li Yang <leoyang.li@nxp.com> --- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index 242fe8bfab17..6b2bfb5c6f32 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -901,6 +901,7 @@ pcie1: pcie@3400000 { <0000 0 0 2 &gic 0 111 0x4>, <0000 0 0 3 &gic 0 112 0x4>, <0000 0 0 4 &gic 0 113 0x4>; + fsl,pcie-scfg = <&scfg 0>; status = "disabled"; }; @@ -927,6 +928,7 @@ pcie2: pcie@3500000 { <0000 0 0 2 &gic 0 121 0x4>, <0000 0 0 3 &gic 0 122 0x4>, <0000 0 0 4 &gic 0 123 0x4>; + fsl,pcie-scfg = <&scfg 1>; status = "disabled"; }; @@ -953,6 +955,7 @@ pcie3: pcie@3600000 { <0000 0 0 2 &gic 0 155 0x4>, <0000 0 0 3 &gic 0 156 0x4>, <0000 0 0 4 &gic 0 157 0x4>; + fsl,pcie-scfg = <&scfg 2>; status = "disabled"; }; -- 2.37.1
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