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    Subject[PATCH 5.4 313/389] pinctrl: qcom: msm8916: Allow CAMSS GP clocks to be muxed
    Date
    From: Nikita Travkin <nikita@trvn.ru>

    commit 44339391c666e46cba522d19c65a6ad1071c68b7 upstream.

    GPIO 31, 32 can be muxed to GCC_CAMSS_GP(1,2)_CLK respectively but the
    function was never assigned to the pingroup (even though the function
    exists already).

    Add this mode to the related pins.

    Fixes: 5373a2c5abb6 ("pinctrl: qcom: Add msm8916 pinctrl driver")
    Signed-off-by: Nikita Travkin <nikita@trvn.ru>
    Link: https://lore.kernel.org/r/20220612145955.385787-4-nikita@trvn.ru
    Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    drivers/pinctrl/qcom/pinctrl-msm8916.c | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    --- a/drivers/pinctrl/qcom/pinctrl-msm8916.c
    +++ b/drivers/pinctrl/qcom/pinctrl-msm8916.c
    @@ -844,8 +844,8 @@ static const struct msm_pingroup msm8916
    PINGROUP(28, pwr_modem_enabled_a, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac),
    PINGROUP(29, cci_i2c, NA, NA, NA, NA, NA, qdss_tracedata_b, NA, atest_combodac),
    PINGROUP(30, cci_i2c, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
    - PINGROUP(31, cci_timer0, NA, NA, NA, NA, NA, NA, NA, NA),
    - PINGROUP(32, cci_timer1, NA, NA, NA, NA, NA, NA, NA, NA),
    + PINGROUP(31, cci_timer0, flash_strobe, NA, NA, NA, NA, NA, NA, NA),
    + PINGROUP(32, cci_timer1, flash_strobe, NA, NA, NA, NA, NA, NA, NA),
    PINGROUP(33, cci_async, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
    PINGROUP(34, pwr_nav_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),
    PINGROUP(35, pwr_crypto_enabled_a, NA, NA, NA, NA, NA, NA, NA, qdss_tracedata_b),

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