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    SubjectRe: [PATCH v3 2/6] dt-binding: phy: Add iMX8MP PCIe PHY binding
    On Thu, Aug 18, 2022 at 03:02:29PM +0800, Richard Zhu wrote:
    > Add i.MX8MP PCIe PHY binding.

    Explain the differences in h/w. The phy is connected to PERST#?

    >
    > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
    > ---
    > .../bindings/phy/fsl,imx8-pcie-phy.yaml | 16 +++++++++++++---
    > 1 file changed, 13 insertions(+), 3 deletions(-)
    >
    > diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
    > index b6421eedece3..692783c7fd69 100644
    > --- a/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
    > +++ b/Documentation/devicetree/bindings/phy/fsl,imx8-pcie-phy.yaml
    > @@ -16,6 +16,7 @@ properties:
    > compatible:
    > enum:
    > - fsl,imx8mm-pcie-phy
    > + - fsl,imx8mp-pcie-phy
    >
    > reg:
    > maxItems: 1
    > @@ -28,11 +29,16 @@ properties:
    > - const: ref
    >
    > resets:
    > - maxItems: 1
    > + minItems: 1
    > + maxItems: 2
    >
    > reset-names:
    > - items:
    > - - const: pciephy
    > + oneOf:
    > + - items: # for iMX8MM
    > + - const: pciephy
    > + - items: # for IMX8MP
    > + - const: pciephy
    > + - const: perst

    This does the same thing:

    minItems: 1
    items:
    - const: pciephy
    - const: perst


    >
    > fsl,refclk-pad-mode:
    > description: |
    > @@ -60,6 +66,10 @@ properties:
    > description: A boolean property indicating the CLKREQ# signal is
    > not supported in the board design (optional)
    >
    > + power-domains:
    > + description: PCIe PHY power domain (optional).
    > + maxItems: 1
    > +
    > required:
    > - "#phy-cells"
    > - compatible
    > --
    > 2.25.1
    >
    >

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