lkml.org 
[lkml]   [2022]   [Aug]   [22]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 03/13] EDAC/synopsys: Add multi-ranked memory support
    Date
    DW uMCTL2 DDRC supports multi-rank memory attached to the controller. If
    so the MSTR.active_ranks field will be set with the populated ranks
    bitfield. It is permitted to have one, two or four ranks activated at a
    time [1]. Since we now have the number of ranks determined in the
    controller configuration detection procedure, it can be easily used for
    accordingly extending the MCI chip-select layer. In case of the ECC errors
    the affected rank will be read from the CE/UE address CSRs [2].

    Note we need to drop the ranks from the total memory size calculation
    since multiple ranks are taken into account by means of the layer[0]
    definition.

    [1] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2)
    Databook, Version 3.91a, October 2020, p.739
    [2] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2)
    Databook, Version 3.91a, October 2020, p.821, p.832

    Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
    ---
    drivers/edac/synopsys_edac.c | 14 ++++----------
    1 file changed, 4 insertions(+), 10 deletions(-)

    diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
    index 90b57986a9b5..872ad9a164a7 100644
    --- a/drivers/edac/synopsys_edac.c
    +++ b/drivers/edac/synopsys_edac.c
    @@ -23,9 +23,6 @@

    #include "edac_module.h"

    -/* Number of cs_rows needed per memory controller */
    -#define SNPS_EDAC_NR_CSROWS 1
    -
    /* Number of channels per memory controller */
    #define SNPS_EDAC_NR_CHANS 1

    @@ -795,7 +792,7 @@ static void snps_handle_error(struct mem_ctl_info *mci, struct snps_ecc_status *

    edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, p->ce_cnt,
    PHYS_PFN(sys), offset_in_page(sys),
    - pinf->syndrome, 0, 0, -1,
    + pinf->syndrome, pinf->sdram.rank, 0, -1,
    priv->message, "");
    }

    @@ -812,7 +809,7 @@ static void snps_handle_error(struct mem_ctl_info *mci, struct snps_ecc_status *

    edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, p->ue_cnt,
    PHYS_PFN(sys), offset_in_page(sys),
    - pinf->syndrome, 0, 0, -1,
    + pinf->syndrome, pinf->sdram.rank, 0, -1,
    priv->message, "");
    }

    @@ -1411,10 +1408,7 @@ static u64 snps_get_sdram_size(struct snps_edac_priv *priv)
    size++;
    }

    - for (i = 0; i < DDR_MAX_RANK_WIDTH; i++) {
    - if (map->rank[i] != DDR_ADDRMAP_UNUSED)
    - size++;
    - }
    + /* Skip the ranks since the multi-rankness is determined by layer[0] */

    return 1ULL << (size + priv->info.dq_width);
    }
    @@ -1468,7 +1462,7 @@ static struct mem_ctl_info *snps_mc_create(struct snps_edac_priv *priv)
    struct mem_ctl_info *mci;

    layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
    - layers[0].size = SNPS_EDAC_NR_CSROWS;
    + layers[0].size = priv->info.ranks;
    layers[0].is_virt_csrow = true;
    layers[1].type = EDAC_MC_LAYER_CHANNEL;
    layers[1].size = SNPS_EDAC_NR_CHANS;
    --
    2.35.1
    \
     
     \ /
      Last update: 2022-08-22 21:22    [W:4.228 / U:0.320 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site