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    Subject[PATCH 05/20] EDAC/synopsys: Fix reading errors count before ECC status
    Date
    Aside with fixing the errors count CSR usage the commit e2932d1f6f05
    ("EDAC/synopsys: Read the error count from the correct register") all of
    the sudden has also changed the order of the errors status check
    procedure. So now the errors handler method first reads the number of CE
    and UE and only then makes sure that any of these errors have actually
    happened. It doesn't make much sense. Let's fix that by getting back the
    procedures order: first check the ECC status, then read the number of
    errors.

    Fixes: e2932d1f6f05 ("EDAC/synopsys: Read the error count from the correct register")
    Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
    ---
    drivers/edac/synopsys_edac.c | 12 ++++++------
    1 file changed, 6 insertions(+), 6 deletions(-)

    diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
    index 873dbc684fe6..14653b799901 100644
    --- a/drivers/edac/synopsys_edac.c
    +++ b/drivers/edac/synopsys_edac.c
    @@ -422,18 +422,18 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv)
    base = priv->baseaddr;
    p = &priv->stat;

    - regval = readl(base + ECC_ERRCNT_OFST);
    - p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK;
    - p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT;
    - if (!p->ce_cnt)
    - goto ue_err;
    -
    regval = readl(base + ECC_STAT_OFST);
    if (!regval)
    return 1;

    p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK);

    + regval = readl(base + ECC_ERRCNT_OFST);
    + p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK;
    + p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT;
    + if (!p->ce_cnt)
    + goto ue_err;
    +
    regval = readl(base + ECC_CEADDR0_OFST);
    p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK);
    regval = readl(base + ECC_CEADDR1_OFST);
    --
    2.35.1
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