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SubjectRe: [PATCH v2 2/3] spi: microchip-core-qspi: Add support for microchip fpga qspi controllers
Hi Krzysztof and Conor,


On Tue, Aug 2, 2022 at 3:56 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 02/08/2022 09:05, Naga Sureshkumar Relli wrote:
> > +
> > + qspi->clk = devm_clk_get(&pdev->dev, NULL);
> > + if (IS_ERR(qspi->clk)) {
> > + dev_err(&pdev->dev, "clock not found.\n");
>
> Same comments as v1.
Ok. I will update it.

Thanks,
Naga Suresshkumar Relli.

>
> > + ret = PTR_ERR(qspi->clk);
> > + goto remove_master;
> > + }
> > +
> > + ret = clk_prepare_enable(qspi->clk);
> > + if (ret) {
> > + dev_err(&pdev->dev, "failed to enable clock\n");
> > + goto remove_master;
> > + }
> > +
> > + init_completion(&qspi->data_completion);
> > + mutex_init(&qspi->op_lock);
> > +
> > + qspi->irq = platform_get_irq(pdev, 0);
> > + if (qspi->irq <= 0) {
> > + ret = qspi->irq;
> > + goto clk_dis_all;
> > + }
> > +
> > + ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr,
> > + IRQF_SHARED, pdev->name, qspi);
> > + if (ret) {
> > + dev_err(&pdev->dev, "request_irq failed %d\n", ret);
> > + goto clk_dis_all;
> > + }
> > +
> > + ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
> > + ctlr->mem_ops = &mchp_coreqspi_mem_ops;
> > + ctlr->setup = mchp_coreqspi_setup_op;
> > + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
> > + SPI_TX_DUAL | SPI_TX_QUAD;
> > + ctlr->dev.of_node = np;
> > +
> > + ret = devm_spi_register_controller(&pdev->dev, ctlr);
> > + if (ret) {
> > + dev_err(&pdev->dev, "spi_register_controller failed\n");
> > + goto clk_dis_all;
> > + }
> > +
> > + return 0;
> > +
> > +clk_dis_all:
> > + clk_disable_unprepare(qspi->clk);
> > +remove_master:
> > + spi_controller_put(ctlr);
> > +
> > + return ret;
> > +}
> > +
> > +static int mchp_coreqspi_remove(struct platform_device *pdev)
> > +{
> > + struct mchp_coreqspi *qspi = platform_get_drvdata(pdev);
> > + u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
> > +
> > + mchp_coreqspi_disable_ints(qspi);
> > + control &= ~CONTROL_ENABLE;
> > + writel_relaxed(control, qspi->regs + REG_CONTROL);
> > + clk_disable_unprepare(qspi->clk);
> > +
> > + return 0;
> > +}
> > +
> > +/*
> > + * Platform driver data structure
>
> Same comments as v1.
>
> > + */
> > +static const struct of_device_id mchp_coreqspi_of_match[] = {
> > + { .compatible = "microchip,mpfs-qspi" },
> > + { .compatible = "microchip,coreqspi-rtl-v2" },
> > + { /* sentinel */ }
> > +};
> > +MODULE_DEVICE_TABLE(of, mchp_coreqspi_of_match);
> > +
> Best regards,
> Krzysztof

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