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SubjectRe: [PATCH 3/3] dt-bindings: bus: Add Freescale i.MX8qxp pixel link MSI bus binding
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On 02/08/2022 09:13, Liu Ying wrote:
> Freescale i.MX8qxp pixel link MSI bus is a simple memory-mapped bus.
> It is used to access peripherals in i.MX8qm/qxp imaging, LVDS, MIPI
> DSI and HDMI TX subsystems, like I2C controller, PWM controller,
> MIPI DSI controller and Control and Status Registers (CSR) module.
>
> Reference simple-pm-bus bindings and add Freescale i.MX8qxp pixel
> link MSI bus specific bindings.
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> .../bus/fsl,imx8qxp-pixel-link-msi-bus.yaml | 84 +++++++++++++++++++
> 1 file changed, 84 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
>
> diff --git a/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
> new file mode 100644
> index 000000000000..24f50535f5c2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml
> @@ -0,0 +1,84 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus

Shouldn't this be interconnect, not a bus? Not only located in
interconnect directory but actually being proper interconnect? Although
you mentioned that the firmware controls it, so maybe that would explain
this being only a resource provider.

You should be sure of it, because later if you want to add proper
interconnect properties (e.g. bandwidth voting, paths) *you will not be
able*. Ever.

> +
> +maintainers:
> + - Liu Ying <victor.liu@nxp.com>
> +
> +description: |
> + i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
> + sitting together with the PHYs. It is not the same as the MSI bus coming
> + from i.MX8 System Controller Unit (SCU) which is used to control power,
> + clock and reset through the i.MX8 Distributed Slave System Controller (DSC).
> +
> + i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
> + that is, MSI clock and AHB clock, need to be enabled so that peripherals
> + connected to the bus can be accessed. Also, the bus is part of a power
> + domain. The power domain needs to be enabled before the peripherals can
> + be accessed.
> +
> + Peripherals in i.MX8qm/qxp imaging, LVDS, MIPI DSI and HDMI TX subsystems,
> + like I2C controller, PWM controller, MIPI DSI controller and Control and
> + Status Registers (CSR) module, are accessed through the bus.
> +
> + The i.MX System Controller Firmware (SCFW) owns and uses the i.MX8qm/qxp
> + pixel link MSI bus controller and does not allow SCFW user to control it.
> + So, the controller's registers cannot be accessed by SCFW user. Hence,
> + the interrupts generated by the controller don't make any sense from SCFW
> + user's point of view.
> +
> +allOf:
> + - $ref: simple-pm-bus.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - fsl,imx8qxp-display-pixel-link-msi-bus
> + - fsl,imx8qm-display-pixel-link-msi-bus
> + - {} # simple-pm-bus, but not listed here to avoid false select

simple-pm-bus must be here. You need to sort out the select instead,
just like we do it for other devices (e.g. primecell).

> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: master gated clock from system
> + - description: AHB clock
> +
> + clock-names:
> + items:
> + - const: msi
> + - const: ahb
> +
> +required:

compatible and reg as well.

> + - clocks
> + - clock-names
> + - power-domains
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/imx8-lpcg.h>
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + bus@56200000 {
> + compatible = "fsl,imx8qxp-display-pixel-link-msi-bus", "simple-pm-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x56200000 0x20000>;

put reg just after compatible.

> + interrupt-parent = <&dc0_irqsteer>;
> + interrupts = <320>;
> + ranges;
> + clocks = <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>,
> + <&dc0_disp_ctrl_link_mst0_lpcg IMX_LPCG_CLK_4>;
> + clock-names = "msi", "ahb";
> + power-domains = <&pd IMX_SC_R_DC_0>;
> + };


Best regards,
Krzysztof

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