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    SubjectRe: [PATCH 2/2] spi: microchip-core-qspi: Add support for microchip fpga qspi controllers
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    On 01/08/2022 11:42, Naga Sureshkumar Relli wrote:
    > Add a driver for Microchip FPGA QSPI controllers. This driver also
    > supports "hard" QSPI controllers on Polarfire SoC.
    >
    > Signed-off-by: Naga Sureshkumar Relli <nagasuresh.relli@microchip.com>

    Thank you for your patch. There is something to discuss/improve.

    > + qspi = spi_controller_get_devdata(ctlr);
    > + platform_set_drvdata(pdev, qspi);
    > +
    > + qspi->regs = devm_platform_ioremap_resource(pdev, 0);
    > + if (IS_ERR(qspi->regs)) {
    > + ret = PTR_ERR(qspi->regs);
    > + goto remove_master;
    > + }
    > +
    > + qspi->clk = devm_clk_get(&pdev->dev, NULL);
    > + if (IS_ERR(qspi->clk)) {
    > + dev_err(&pdev->dev, "clock not found.\n");
    > + ret = PTR_ERR(qspi->clk);

    dev_err_probe() for the two of above.

    > + goto remove_master;
    > + }
    > +
    > + ret = clk_prepare_enable(qspi->clk);
    > + if (ret) {
    > + dev_err(&pdev->dev, "failed to enable clock\n");
    > + goto remove_master;
    > + }
    > +
    > + init_completion(&qspi->data_completion);
    > + mutex_init(&qspi->op_lock);
    > +
    > + qspi->irq = platform_get_irq(pdev, 0);
    > + if (qspi->irq <= 0) {
    > + ret = qspi->irq;
    > + goto clk_dis_all;
    > + }
    > +
    > + ret = devm_request_irq(&pdev->dev, qspi->irq, mchp_coreqspi_isr,
    > + 0, pdev->name, qspi);
    > + if (ret != 0) {
    > + dev_err(&pdev->dev, "request_irq failed %d\n", ret);
    > + goto clk_dis_all;
    > + }
    > +
    > + ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
    > + ctlr->mem_ops = &mchp_coreqspi_mem_ops;
    > + ctlr->setup = mchp_coreqspi_setup_op;
    > + ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
    > + SPI_TX_DUAL | SPI_TX_QUAD;
    > + ctlr->dev.of_node = np;
    > +
    > + ret = devm_spi_register_controller(&pdev->dev, ctlr);
    > + if (ret) {
    > + dev_err(&pdev->dev, "spi_register_controller failed\n");
    > + goto clk_dis_all;
    > + }
    > +
    > + return 0;
    > +
    > +clk_dis_all:
    > + clk_disable_unprepare(qspi->clk);
    > +remove_master:
    > + spi_controller_put(ctlr);
    > +
    > + return ret;
    > +}
    > +
    > +static int mchp_coreqspi_remove(struct platform_device *pdev)
    > +{
    > + struct mchp_coreqspi *qspi = platform_get_drvdata(pdev);
    > + u32 control = readl_relaxed(qspi->regs + REG_CONTROL);
    > +
    > + mchp_coreqspi_disable_ints(qspi);
    > + control &= ~CONTROL_ENABLE;
    > + writel_relaxed(control, qspi->regs + REG_CONTROL);
    > + clk_disable_unprepare(qspi->clk);
    > +
    > + return 0;
    > +}
    > +
    > +/*
    > + * Platform driver data structure
    > + */

    Drop such comments.

    > +static const struct of_device_id mchp_coreqspi_of_match[] = {
    > + { .compatible = "microchip,mpfs-qspi" },
    > + { .compatible = "microchip,coreqspi-rtl-v2" },
    > + { /* sentinel */ }
    > +};
    > +MODULE_DEVICE_TABLE(of, mchp_coreqspi_of_match);
    > +
    > +static struct platform_driver mchp_coreqspi_driver = {
    > + .probe = mchp_coreqspi_probe,
    > + .driver = {
    > + .name = "microchip,mpfs-qspi",
    > + .of_match_table = mchp_coreqspi_of_match,
    > + },
    > + .remove = mchp_coreqspi_remove,
    > +};
    > +module_platform_driver(mchp_coreqspi_driver);
    > +
    > +MODULE_AUTHOR("Naga Sureshkumar Relli <nagasuresh.relli@microchip.com");
    > +MODULE_DESCRIPTION("Microchip coreQSPI QSPI controller driver");
    > +MODULE_LICENSE("GPL");


    Best regards,
    Krzysztof

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