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    Subject[PATCH 5.10 299/545] clk: qcom: ipq8074: set BRANCH_HALT_DELAY flag for UBI clocks
    Date
    From: Robert Marko <robimarko@gmail.com>

    [ Upstream commit 2bd357e698207e2e65db03007e4be65bf9d6a7b3 ]

    Currently, attempting to enable the UBI clocks will cause the stuck at
    off warning to be printed and clk_enable will fail.

    [ 14.936694] gcc_ubi1_ahb_clk status stuck at 'off'

    Downstream 5.4 QCA kernel has fixed this by seting the BRANCH_HALT_DELAY
    flag on UBI clocks, so lets do the same.

    Fixes: 5736294aef83 ("clk: qcom: ipq8074: add NSS clocks")
    Signed-off-by: Robert Marko <robimarko@gmail.com>
    Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
    Link: https://lore.kernel.org/r/20220515210048.483898-6-robimarko@gmail.com
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/clk/qcom/gcc-ipq8074.c | 10 ++++++++++
    1 file changed, 10 insertions(+)

    diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
    index f1017f2e61bd..2c2ecfc5e61f 100644
    --- a/drivers/clk/qcom/gcc-ipq8074.c
    +++ b/drivers/clk/qcom/gcc-ipq8074.c
    @@ -3354,6 +3354,7 @@ static struct clk_branch gcc_nssnoc_ubi1_ahb_clk = {

    static struct clk_branch gcc_ubi0_ahb_clk = {
    .halt_reg = 0x6820c,
    + .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    .enable_reg = 0x6820c,
    .enable_mask = BIT(0),
    @@ -3371,6 +3372,7 @@ static struct clk_branch gcc_ubi0_ahb_clk = {

    static struct clk_branch gcc_ubi0_axi_clk = {
    .halt_reg = 0x68200,
    + .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    .enable_reg = 0x68200,
    .enable_mask = BIT(0),
    @@ -3388,6 +3390,7 @@ static struct clk_branch gcc_ubi0_axi_clk = {

    static struct clk_branch gcc_ubi0_nc_axi_clk = {
    .halt_reg = 0x68204,
    + .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    .enable_reg = 0x68204,
    .enable_mask = BIT(0),
    @@ -3405,6 +3408,7 @@ static struct clk_branch gcc_ubi0_nc_axi_clk = {

    static struct clk_branch gcc_ubi0_core_clk = {
    .halt_reg = 0x68210,
    + .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    .enable_reg = 0x68210,
    .enable_mask = BIT(0),
    @@ -3422,6 +3426,7 @@ static struct clk_branch gcc_ubi0_core_clk = {

    static struct clk_branch gcc_ubi0_mpt_clk = {
    .halt_reg = 0x68208,
    + .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    .enable_reg = 0x68208,
    .enable_mask = BIT(0),
    @@ -3439,6 +3444,7 @@ static struct clk_branch gcc_ubi0_mpt_clk = {

    static struct clk_branch gcc_ubi1_ahb_clk = {
    .halt_reg = 0x6822c,
    + .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    .enable_reg = 0x6822c,
    .enable_mask = BIT(0),
    @@ -3456,6 +3462,7 @@ static struct clk_branch gcc_ubi1_ahb_clk = {

    static struct clk_branch gcc_ubi1_axi_clk = {
    .halt_reg = 0x68220,
    + .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    .enable_reg = 0x68220,
    .enable_mask = BIT(0),
    @@ -3473,6 +3480,7 @@ static struct clk_branch gcc_ubi1_axi_clk = {

    static struct clk_branch gcc_ubi1_nc_axi_clk = {
    .halt_reg = 0x68224,
    + .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    .enable_reg = 0x68224,
    .enable_mask = BIT(0),
    @@ -3490,6 +3498,7 @@ static struct clk_branch gcc_ubi1_nc_axi_clk = {

    static struct clk_branch gcc_ubi1_core_clk = {
    .halt_reg = 0x68230,
    + .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    .enable_reg = 0x68230,
    .enable_mask = BIT(0),
    @@ -3507,6 +3516,7 @@ static struct clk_branch gcc_ubi1_core_clk = {

    static struct clk_branch gcc_ubi1_mpt_clk = {
    .halt_reg = 0x68228,
    + .halt_check = BRANCH_HALT_DELAY,
    .clkr = {
    .enable_reg = 0x68228,
    .enable_mask = BIT(0),
    --
    2.35.1


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