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    Subject[PATCH 5.10 204/545] drm/vc4: hdmi: Correct HDMI timing registers for interlaced modes
    Date
    From: Dave Stevenson <dave.stevenson@raspberrypi.com>

    [ Upstream commit fb10dc451c0f15e3c19798a2f41d357f3f7576f5 ]

    For interlaced modes the timings were not being correctly
    programmed into the HDMI block, so correct them.

    Fixes: 8323989140f3 ("drm/vc4: hdmi: Support the BCM2711 HDMI controllers")
    Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
    Link: https://lore.kernel.org/r/20220613144800.326124-33-maxime@cerno.tech
    Signed-off-by: Maxime Ripard <maxime@cerno.tech>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/gpu/drm/vc4/vc4_hdmi.c | 8 ++++----
    1 file changed, 4 insertions(+), 4 deletions(-)

    --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
    +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
    @@ -565,13 +565,13 @@ static void vc5_hdmi_set_timings(struct
    VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
    VC5_HDMI_VERTA_VFP) |
    VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
    - u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
    - VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
    - interlaced,
    + u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
    + VC5_HDMI_VERTB_VSPO) |
    + VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
    VC4_HDMI_VERTB_VBP));
    u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
    VC4_SET_FIELD(mode->crtc_vtotal -
    - mode->crtc_vsync_end,
    + mode->crtc_vsync_end - interlaced,
    VC4_HDMI_VERTB_VBP));

    HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);

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