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    Subject[PATCH 5.19 0702/1157] iio: gyro: adis16130: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit ff3211b2ba9afac80ceb795d148831dd879b30b7 ]

    ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
    on platforms with 128 byte cachelines above L1. Switch to the updated
    IIO_DMA_MINALIGN definition.

    Fixes: 8e67875141b2 ("staging:iio:gyro: adis16130 cleanup, move to abi and bug fixes.")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-74-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/gyro/adis16130.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/iio/gyro/adis16130.c b/drivers/iio/gyro/adis16130.c
    index b9c952e65b55..33cde9e6fca5 100644
    --- a/drivers/iio/gyro/adis16130.c
    +++ b/drivers/iio/gyro/adis16130.c
    @@ -41,7 +41,7 @@
    struct adis16130_state {
    struct spi_device *us;
    struct mutex buf_lock;
    - u8 buf[4] ____cacheline_aligned;
    + u8 buf[4] __aligned(IIO_DMA_MINALIGN);
    };

    static int adis16130_spi_read(struct iio_dev *indio_dev, u8 reg_addr, u32 *val)
    --
    2.35.1


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