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    Subject[PATCH 5.19 0697/1157] iio: frequency: admv1013: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit b3f3f8d264b9be0cb3e50e89e3f8789a948a43bb ]

    ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
    on platforms with 128 byte cachelines above L1. Switch to the updated
    IIO_DMA_MINALIGN definition.

    Fixes: da35a7b526d9 ("iio: frequency: admv1013: add support for ADMV1013")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Cc: Antoniu Miclaus <antoniu.miclaus@analog.com>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-69-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/frequency/admv1013.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/iio/frequency/admv1013.c b/drivers/iio/frequency/admv1013.c
    index b0e1f6571afb..ed8167271358 100644
    --- a/drivers/iio/frequency/admv1013.c
    +++ b/drivers/iio/frequency/admv1013.c
    @@ -100,7 +100,7 @@ struct admv1013_state {
    unsigned int input_mode;
    unsigned int quad_se_mode;
    bool det_en;
    - u8 data[3] ____cacheline_aligned;
    + u8 data[3] __aligned(IIO_DMA_MINALIGN);
    };

    static int __admv1013_spi_read(struct admv1013_state *st, unsigned int reg,
    --
    2.35.1


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