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    Subject[PATCH 5.19 0704/1157] iio: gyro: fxas210002c: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit 3aafe923987cb4a15e16f03c6185ed4b6a78ca00 ]

    ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
    on platforms with 128 byte cachelines above L1. Switch to the updated
    IIO_DMA_MINALIGN definition.

    Updated the comment to 'may' require.

    Fixes: a0701b6263ae ("iio: gyro: add core driver for fxas21002c")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Reviewed-by: Rui Miguel Silva <rui.silva@linaro.org>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-76-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/gyro/fxas21002c_core.c | 6 +++---
    1 file changed, 3 insertions(+), 3 deletions(-)

    diff --git a/drivers/iio/gyro/fxas21002c_core.c b/drivers/iio/gyro/fxas21002c_core.c
    index 0923fd793492..a36d71d9e3ea 100644
    --- a/drivers/iio/gyro/fxas21002c_core.c
    +++ b/drivers/iio/gyro/fxas21002c_core.c
    @@ -150,10 +150,10 @@ struct fxas21002c_data {
    struct regulator *vddio;

    /*
    - * DMA (thus cache coherency maintenance) requires the
    - * transfer buffers to live in their own cache lines.
    + * DMA (thus cache coherency maintenance) may require the
    + * transfer buffers live in their own cache lines.
    */
    - s16 buffer[8] ____cacheline_aligned;
    + s16 buffer[8] __aligned(IIO_DMA_MINALIGN);
    };

    enum fxas21002c_channel_index {
    --
    2.35.1


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