Messages in this thread Patch in this message | | | From | Greg Kroah-Hartman <> | Subject | [PATCH 5.19 0656/1157] iio: adc: mcp320x: Fix alignment for DMA safety | Date | Mon, 15 Aug 2022 20:00:12 +0200 |
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From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
[ Upstream commit e770f78036ce4327caf285873f4b20564a8b4f0f ]
____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition.
Worth noting the fixes tag refers to the same issue being observed on a platform that probably had only 64 byte cachelines.
Fixes: 0e81bc99a082 ("iio: mcp320x: Fix occasional incorrect readings") Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Cc: Michael Welling <mwelling@ieee.org> Acked-by: Nuno Sá <nuno.sa@analog.com> Link: https://lore.kernel.org/r/20220508175712.647246-28-jic23@kernel.org Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/iio/adc/mcp320x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iio/adc/mcp320x.c b/drivers/iio/adc/mcp320x.c index b4c69acb33e3..f3b81798b3c9 100644 --- a/drivers/iio/adc/mcp320x.c +++ b/drivers/iio/adc/mcp320x.c @@ -92,7 +92,7 @@ struct mcp320x { struct mutex lock; const struct mcp320x_chip_info *chip_info; - u8 tx_buf ____cacheline_aligned; + u8 tx_buf __aligned(IIO_DMA_MINALIGN); u8 rx_buf[4]; }; -- 2.35.1
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