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    Subject[PATCH 5.19 0683/1157] iio: dac: ad5770r: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit 27f2261d16d01858b8e5baca5a1a515b040429c4 ]

    ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
    on platforms with 128 byte cachelines above L1. Switch to the updated
    IIO_DMA_MINALIGN definition.

    Fixes: cbbb819837f6 ("iio: dac: ad5770r: Add AD5770R support")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Cc: Alexandru Tachici <alexandru.tachici@analog.com>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-55-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/dac/ad5770r.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/iio/dac/ad5770r.c b/drivers/iio/dac/ad5770r.c
    index 7e2fd32e993a..f66d67402e43 100644
    --- a/drivers/iio/dac/ad5770r.c
    +++ b/drivers/iio/dac/ad5770r.c
    @@ -140,7 +140,7 @@ struct ad5770r_state {
    bool ch_pwr_down[AD5770R_MAX_CHANNELS];
    bool internal_ref;
    bool external_res;
    - u8 transf_buf[2] ____cacheline_aligned;
    + u8 transf_buf[2] __aligned(IIO_DMA_MINALIGN);
    };

    static const struct regmap_config ad5770r_spi_regmap_config = {
    --
    2.35.1


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