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    Subject[PATCH 5.19 0682/1157] iio: dac: ad5766: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit c32be7f035ae430ba9c142b03ceb9f935b09ed6b ]

    ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
    on platforms with 128 byte cachelines above L1. Switch to the updated
    IIO_DMA_MINALIGN definition.

    Fixes: fd9373e41b9b ("iio: dac: ad5766: add driver support for AD5766")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-54-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/dac/ad5766.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    diff --git a/drivers/iio/dac/ad5766.c b/drivers/iio/dac/ad5766.c
    index 43189af2fb1f..899894523752 100644
    --- a/drivers/iio/dac/ad5766.c
    +++ b/drivers/iio/dac/ad5766.c
    @@ -123,7 +123,7 @@ struct ad5766_state {
    u32 d32;
    u16 w16[2];
    u8 b8[4];
    - } data[3] ____cacheline_aligned;
    + } data[3] __aligned(IIO_DMA_MINALIGN);
    };

    struct ad5766_span_tbl {
    --
    2.35.1


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