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    Subject[PATCH 5.19 0678/1157] iio: dac: ad5686: Fix alignment for DMA safety
    Date
    From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

    [ Upstream commit 444e38927d9af093de7cdc6afbb7afdc3485da2d ]

    ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
    on platforms with 128 byte cachelines above L1. Switch to the updated
    IIO_DMA_MINALIGN definition.

    Update the comment to include 'may'.

    Fixes: 0357e488b825 ("iio:dac:ad5686: Refactor the driver")
    Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
    Acked-by: Nuno Sá <nuno.sa@analog.com>
    Link: https://lore.kernel.org/r/20220508175712.647246-50-jic23@kernel.org
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/iio/dac/ad5686.h | 6 ++++--
    1 file changed, 4 insertions(+), 2 deletions(-)

    diff --git a/drivers/iio/dac/ad5686.h b/drivers/iio/dac/ad5686.h
    index cd5fff9e9d53..b7ade3a6b9b6 100644
    --- a/drivers/iio/dac/ad5686.h
    +++ b/drivers/iio/dac/ad5686.h
    @@ -13,6 +13,8 @@
    #include <linux/mutex.h>
    #include <linux/kernel.h>

    +#include <linux/iio/iio.h>
    +
    #define AD5310_CMD(x) ((x) << 12)

    #define AD5683_DATA(x) ((x) << 4)
    @@ -137,7 +139,7 @@ struct ad5686_state {
    struct mutex lock;

    /*
    - * DMA (thus cache coherency maintenance) requires the
    + * DMA (thus cache coherency maintenance) may require the
    * transfer buffers to live in their own cache lines.
    */

    @@ -145,7 +147,7 @@ struct ad5686_state {
    __be32 d32;
    __be16 d16;
    u8 d8[4];
    - } data[3] ____cacheline_aligned;
    + } data[3] __aligned(IIO_DMA_MINALIGN);
    };


    --
    2.35.1


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