Messages in this thread | | | Date | Wed, 17 Aug 2022 00:53:33 +0300 | Subject | Re: [PATCH v2 7/7] dt-bindings: net: dsa: mediatek,mt7530: update binding description | From | Arınç ÜNAL <> |
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On 17.08.2022 00:25, Rob Herring wrote: > On Sat, Aug 13, 2022 at 06:44:15PM +0300, Arınç ÜNAL wrote: >> Update the description of the binding. >> >> - Describe the switches, which SoCs they are in, or if they are standalone. >> - Explain the various ways of configuring MT7530's port 5. >> - Remove phy-mode = "rgmii-txid" from description. Same code path is >> followed for delayed rgmii and rgmii phy-mode on mtk_eth_soc.c. >> >> Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com> >> --- >> .../bindings/net/dsa/mediatek,mt7530.yaml | 97 ++++++++++++------- >> 1 file changed, 62 insertions(+), 35 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml >> index 530ef5a75a2f..cf6340d072df 100644 >> --- a/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml >> +++ b/Documentation/devicetree/bindings/net/dsa/mediatek,mt7530.yaml >> @@ -13,41 +13,68 @@ maintainers: >> - Sean Wang <sean.wang@mediatek.com> >> >> description: | >> - Port 5 of mt7530 and mt7621 switch is muxed between: >> - 1. GMAC5: GMAC5 can interface with another external MAC or PHY. >> - 2. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC >> - of the SOC. Used in many setups where port 0/4 becomes the WAN port. >> - Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to >> - GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not >> - connected to external component! >> - >> - Port 5 modes/configurations: >> - 1. Port 5 is disabled and isolated: An external phy can interface to the 2nd >> - GMAC of the SOC. >> - In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd >> - GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC! >> - 2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC. >> - It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode >> - and RGMII delay. >> - 3. Port 5 is muxed to GMAC5 and can interface to an external phy. >> - Port 5 becomes an extra switch port. >> - Only works on platform where external phy TX<->RX lines are swapped. >> - Like in the Ubiquiti ER-X-SFP. >> - 4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port. >> - Currently a 2nd CPU port is not supported by DSA code. >> - >> - Depending on how the external PHY is wired: >> - 1. normal: The PHY can only connect to 2nd GMAC but not to the switch >> - 2. swapped: RGMII TX, RX are swapped; external phy interface with the switch as >> - a ethernet port. But can't interface to the 2nd GMAC. >> - >> - Based on the DT the port 5 mode is configured. >> - >> - Driver tries to lookup the phy-handle of the 2nd GMAC of the master device. >> - When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2. >> - phy-mode must be set, see also example 2 below! >> - * mt7621: phy-mode = "rgmii-txid"; >> - * mt7623: phy-mode = "rgmii"; >> + There are two versions of MT7530, standalone and in a multi-chip module. >> + >> + MT7530 is a part of the multi-chip module in MT7620AN, MT7620DA, MT7620DAN, >> + MT7620NN, MT7621AT, MT7621DAT, MT7621ST and MT7623AI SoCs. >> + >> + MT7530 in MT7620AN, MT7620DA, MT7620DAN and MT7620NN SoCs has got 10/100 PHYs > > s/got //
Can't use British English on bindings? :)
> >> + and the switch registers are directly mapped into SoC's memory map rather than >> + using MDIO. There is currently no support for this. > > No support in the binding or driver? Driver capabilities are relevant to > the binding.
In the driver. Also, did you mean irrelevant? Should I remove this part from the binding?
> >> + >> + There is only the standalone version of MT7531. >> + >> + Port 5 on MT7530 has got various ways of configuration. > > s/got // > >> + >> + For standalone MT7530: >> + >> + - Port 5 can be used as a CPU port. >> + >> + - PHY 0 or 4 of the switch can be muxed to connect to the gmac of the SoC >> + which port 5 is wired to. Usually used for connecting the wan port >> + directly to the CPU to achieve 2 Gbps routing in total. >> + >> + The driver looks up the reg on the ethernet-phy node which the phy-handle >> + property refers to on the gmac node to mux the specified phy. >> + >> + The driver requires the gmac of the SoC to have "mediatek,eth-mac" as the >> + compatible string and the reg must be 1. So, for now, only gmac1 of an >> + MediaTek SoC can benefit this. Banana Pi BPI-R2 suits this. >> + Check out example 5 for a similar configuration. >> + >> + - Port 5 can be wired to an external phy. Port 5 becomes a DSA slave. >> + Check out example 7 for a similar configuration. >> + >> + For multi-chip module MT7530: >> + >> + - Port 5 can be used as a CPU port. >> + >> + - PHY 0 or 4 of the switch can be muxed to connect to gmac1 of the SoC. >> + Usually used for connecting the wan port directly to the CPU to achieve 2 >> + Gbps routing in total. >> + >> + The driver looks up the reg on the ethernet-phy node which the phy-handle >> + property refers to on the gmac node to mux the specified phy. >> + >> + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. >> + Check out example 5. >> + >> + - In case of an external phy wired to gmac1 of the SoC, port 5 must not be >> + enabled. >> + >> + In case of muxing PHY 0 or 4, the external phy must not be enabled. >> + >> + For the MT7621 SoCs, rgmii2 group must be claimed with rgmii2 function. >> + Check out example 6. >> + >> + - Port 5 can be muxed to an external phy. Port 5 becomes a DSA slave. >> + The external phy must be wired TX to TX to gmac1 of the SoC for this to >> + work. Ubiquiti EdgeRouter X SFP is wired this way. >> + >> + Muxing PHY 0 or 4 won't work when the external phy is connected TX to TX. >> + >> + For the MT7621 SoCs, rgmii2 group must be claimed with gpio function. >> + Check out example 7. >> >> properties: >> compatible: >> -- >> 2.34.1 >> >>
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