lkml.org 
[lkml]   [2022]   [Aug]   [16]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
    Patch in this message
    /
    From
    Subject[PATCH 5.19 0782/1157] phy: qcom-qmp: fix the QSERDES_V5_COM_CMN_MODE register
    Date
    From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

    [ Upstream commit 488987b2d5cade4e7680f7e81590435a848d1fa9 ]

    Change QSERDES_V5_COM_CMN_MODE to be defined to 0x1a0 rather than 0x1a4.
    The only user of this register name (sm8450_qmp_gen4x2_pcie_serdes_tbl)
    should use the 0x1a0 register, as stated in the downstream dtsi tree.

    Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support")
    Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
    Link: https://lore.kernel.org/r/20220705094320.1313312-2-dmitry.baryshkov@linaro.org
    Signed-off-by: Vinod Koul <vkoul@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/phy/qualcomm/phy-qcom-qmp.h | 3 ++-
    1 file changed, 2 insertions(+), 1 deletion(-)

    diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
    index 06b2556ed93a..b9a91520439c 100644
    --- a/drivers/phy/qualcomm/phy-qcom-qmp.h
    +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
    @@ -1116,7 +1116,8 @@
    #define QSERDES_V5_COM_CORE_CLK_EN 0x174
    #define QSERDES_V5_COM_CMN_CONFIG 0x17c
    #define QSERDES_V5_COM_CMN_MISC1 0x19c
    -#define QSERDES_V5_COM_CMN_MODE 0x1a4
    +#define QSERDES_V5_COM_CMN_MODE 0x1a0
    +#define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4
    #define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8
    #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac
    #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0
    --
    2.35.1


    \
     
     \ /
      Last update: 2022-08-16 06:43    [W:4.139 / U:1.084 seconds]
    ©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site