lkml.org 
[lkml]   [2022]   [Aug]   [15]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
From
SubjectRe: [PATCHv6 04/11] x86/mm: Handle LAM on context switch
On Mon, Aug 15, 2022 at 03:42:25PM +0200, Peter Zijlstra wrote:
> On Mon, Aug 15, 2022 at 07:17:56AM +0300, Kirill A. Shutemov wrote:
> > diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
> > index c1e31e9a85d7..fdc0b69b5da7 100644
> > --- a/arch/x86/mm/tlb.c
> > +++ b/arch/x86/mm/tlb.c
> > @@ -154,17 +154,18 @@ static inline u16 user_pcid(u16 asid)
> > return ret;
> > }
> >
> > -static inline unsigned long build_cr3(pgd_t *pgd, u16 asid)
> > +static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam)
> > {
> > if (static_cpu_has(X86_FEATURE_PCID)) {
> > - return __sme_pa(pgd) | kern_pcid(asid);
> > + return __sme_pa(pgd) | kern_pcid(asid) | lam;
> > } else {
> > VM_WARN_ON_ONCE(asid != 0);
> > - return __sme_pa(pgd);
> > + return __sme_pa(pgd) | lam;
> > }
> > }
> >
> > -static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
> > +static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid,
> > + unsigned long lam)
> > {
> > VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
> > /*
> > @@ -173,7 +174,7 @@ static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid)
> > * boot because all CPU's the have same capabilities:
> > */
> > VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
> > - return __sme_pa(pgd) | kern_pcid(asid) | CR3_NOFLUSH;
> > + return __sme_pa(pgd) | kern_pcid(asid) | lam | CR3_NOFLUSH;
> > }
>
> Looking at this; I wonder if we want something like this:
>
> --- a/arch/x86/mm/tlb.c
> +++ b/arch/x86/mm/tlb.c
> @@ -157,6 +157,7 @@ static inline u16 user_pcid(u16 asid)
> static inline unsigned long build_cr3(pgd_t *pgd, u16 asid, unsigned long lam)
> {
> if (static_cpu_has(X86_FEATURE_PCID)) {
> + VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
> return __sme_pa(pgd) | kern_pcid(asid) | lam;
> } else {
> VM_WARN_ON_ONCE(asid != 0);
> @@ -167,14 +168,13 @@ static inline unsigned long build_cr3(pg
> static inline unsigned long build_cr3_noflush(pgd_t *pgd, u16 asid,
> unsigned long lam)
> {
> - VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
> /*
> * Use boot_cpu_has() instead of this_cpu_has() as this function
> * might be called during early boot. This should work even after
> * boot because all CPU's the have same capabilities:
> */
> VM_WARN_ON_ONCE(!boot_cpu_has(X86_FEATURE_PCID));
> - return __sme_pa(pgd) | kern_pcid(asid) | lam | CR3_NOFLUSH;
> + return build_cr3(pgd, asid, lam) | CR3_NOFLUSH;
> }

Looks sane, but seems unrelated to the patch. Is it okay to fold it
anyway?

--
Kiryl Shutsemau / Kirill A. Shutemov

\
 
 \ /
  Last update: 2022-08-15 19:36    [W:0.082 / U:0.076 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site