Messages in this thread | | | From | Stephane Eranian <> | Date | Mon, 15 Aug 2022 12:42:23 -0700 | Subject | Re: [PATCH 04/13] x86/cpufeatures: Add LbrExtV2 feature bit |
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Hi,
On Mon, Aug 15, 2022 at 4:27 AM Peter Zijlstra <peterz@infradead.org> wrote: > > On Thu, Aug 11, 2022 at 05:59:52PM +0530, Sandipan Das wrote: > > CPUID leaf 0x80000022 i.e. ExtPerfMonAndDbg advertises some new performance > > monitoring features for AMD processors. > > > > Bit 1 of EAX indicates support for Last Branch Record Extension Version 2 > > (LbrExtV2) features. If found to be set during PMU initialization, the EBX > > bits of the same leaf can be used to determine the number of available LBR > > entries. > > > > For better utilization of feature words, LbrExtV2 is added as a scattered > > feature bit. > > > > Signed-off-by: Sandipan Das <sandipan.das@amd.com> > > --- > > arch/x86/include/asm/cpufeatures.h | 2 +- > > arch/x86/kernel/cpu/scattered.c | 1 + > > 2 files changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > > index 393f2bbb5e3a..e3fa476a24b0 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -96,7 +96,7 @@ > > #define X86_FEATURE_SYSCALL32 ( 3*32+14) /* "" syscall in IA32 userspace */ > > #define X86_FEATURE_SYSENTER32 ( 3*32+15) /* "" sysenter in IA32 userspace */ > > #define X86_FEATURE_REP_GOOD ( 3*32+16) /* REP microcode works well */ > > -/* FREE! ( 3*32+17) */ > > +#define X86_FEATURE_LBREXT_V2 ( 3*32+17) /* AMD Last Branch Record Extension Version 2 */ > > #define X86_FEATURE_LFENCE_RDTSC ( 3*32+18) /* "" LFENCE synchronizes RDTSC */ > > #define X86_FEATURE_ACC_POWER ( 3*32+19) /* AMD Accumulated Power Mechanism */ > > #define X86_FEATURE_NOPL ( 3*32+20) /* The NOPL (0F 1F) instructions */ > > diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c > > index dbaa8326d6f2..6be46dffddbf 100644 > > --- a/arch/x86/kernel/cpu/scattered.c > > +++ b/arch/x86/kernel/cpu/scattered.c > > @@ -44,6 +44,7 @@ static const struct cpuid_bit cpuid_bits[] = { > > { X86_FEATURE_PROC_FEEDBACK, CPUID_EDX, 11, 0x80000007, 0 }, > > { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, > > { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, > > + { X86_FEATURE_LBREXT_V2, CPUID_EAX, 1, 0x80000022, 0 }, > > { 0, 0, 0, 0, 0 } > > }; > > Would LBR_V2 work at all? It being a new version already seems to imply > extention, no? Then again, I suppose there's an argument to be had for > avoiding confusion vs the Intel LBR thing.. Couldn't you have called > this BRS_V2 :-) > I believe it is called v2 because there was already a LBR in previous generations, however it was 1-deep and it was not connected to the PMU like this one. The public PPR mentions it (MSR 0x1DB/0x1DC, Last Branch From IP, Last Branch To IP). See for instance the PPR for Fam17h model 71h: https://www.amd.com/system/files/TechDocs/56176_ppr_Family_17h_Model_71h_B0_pub_Rev_3.06.zip
BRS is a model specific feature for Zen3.
LBRv2 is a great improvement including over Zen3 BRS.
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