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    Subject[PATCH 5.15 460/779] PCI: dwc: Add unroll iATU space support to dw_pcie_disable_atu()
    Date
    From: Serge Semin <Sergey.Semin@baikalelectronics.ru>

    [ Upstream commit d1cf738f2b65a5640234e1da90a68d3523fbed83 ]

    dw_pcie_disable_atu() was introduced by f8aed6ec624f ("PCI: dwc:
    designware: Add EP mode support") and supported only the viewport version
    of the iATU CSRs.

    DW PCIe IP cores v4.80a and newer also support unrolled iATU/eDMA space.
    Callers of dw_pcie_disable_atu(), including pci_epc_ops.clear_bar(),
    pci_epc_ops.unmap_addr(), and dw_pcie_setup_rc(), don't work correctly when
    it is enabled.

    Add dw_pcie_disable_atu() support for controllers with unrolled iATU CSRs
    enabled.

    [bhelgaas: commit log]
    Fixes: f8aed6ec624f ("PCI: dwc: designware: Add EP mode support")
    Link: https://lore.kernel.org/r/20220624143428.8334-3-Sergey.Semin@baikalelectronics.ru
    Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
    Reviewed-by: Rob Herring <robh@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/pci/controller/dwc/pcie-designware.c | 16 +++++++++++++---
    1 file changed, 13 insertions(+), 3 deletions(-)

    diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
    index 3254f60d1713..ff74ddf2cc35 100644
    --- a/drivers/pci/controller/dwc/pcie-designware.c
    +++ b/drivers/pci/controller/dwc/pcie-designware.c
    @@ -491,7 +491,7 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, u8 func_no, int index,
    void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
    enum dw_pcie_region_type type)
    {
    - int region;
    + u32 region;

    switch (type) {
    case DW_PCIE_REGION_INBOUND:
    @@ -504,8 +504,18 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
    return;
    }

    - dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
    - dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
    + if (pci->iatu_unroll_enabled) {
    + if (region == PCIE_ATU_REGION_INBOUND) {
    + dw_pcie_writel_ib_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
    + ~(u32)PCIE_ATU_ENABLE);
    + } else {
    + dw_pcie_writel_ob_unroll(pci, index, PCIE_ATU_UNR_REGION_CTRL2,
    + ~(u32)PCIE_ATU_ENABLE);
    + }
    + } else {
    + dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
    + dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~(u32)PCIE_ATU_ENABLE);
    + }
    }

    int dw_pcie_wait_for_link(struct dw_pcie *pci)
    --
    2.35.1


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