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    Subject[PATCH 5.15 404/779] phy: samsung: exynosautov9-ufs: correct TSRV register configurations
    Date
    From: Chanho Park <chanho61.park@samsung.com>

    [ Upstream commit f7fdc4db071f7ee7d408ea3f083222a060c76623 ]

    For exynos auto v9's UFS MPHY, We should use 0x50 offset of TSRV register
    configurations. So, it must be

    s/PHY_TRSV_REG_CFG/PHY_TRSV_REG_CFG_AUTOV9/g

    Fixes: d64519249e1d ("phy: samsung-ufs: support exynosauto ufs phy driver")
    Signed-off-by: Chanho Park <chanho61.park@samsung.com>
    Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
    Link: https://lore.kernel.org/r/20220603050536.61957-1-chanho61.park@samsung.com
    Signed-off-by: Vinod Koul <vkoul@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    drivers/phy/samsung/phy-exynosautov9-ufs.c | 18 +++++++++---------
    1 file changed, 9 insertions(+), 9 deletions(-)

    diff --git a/drivers/phy/samsung/phy-exynosautov9-ufs.c b/drivers/phy/samsung/phy-exynosautov9-ufs.c
    index 36398a15c2db..d043dfdb598a 100644
    --- a/drivers/phy/samsung/phy-exynosautov9-ufs.c
    +++ b/drivers/phy/samsung/phy-exynosautov9-ufs.c
    @@ -31,22 +31,22 @@ static const struct samsung_ufs_phy_cfg exynosautov9_pre_init_cfg[] = {
    PHY_COMN_REG_CFG(0x023, 0xc0, PWR_MODE_ANY),
    PHY_COMN_REG_CFG(0x023, 0x00, PWR_MODE_ANY),

    - PHY_TRSV_REG_CFG(0x042, 0x5d, PWR_MODE_ANY),
    - PHY_TRSV_REG_CFG(0x043, 0x80, PWR_MODE_ANY),
    + PHY_TRSV_REG_CFG_AUTOV9(0x042, 0x5d, PWR_MODE_ANY),
    + PHY_TRSV_REG_CFG_AUTOV9(0x043, 0x80, PWR_MODE_ANY),

    END_UFS_PHY_CFG,
    };

    /* Calibration for HS mode series A/B */
    static const struct samsung_ufs_phy_cfg exynosautov9_pre_pwr_hs_cfg[] = {
    - PHY_TRSV_REG_CFG(0x032, 0xbc, PWR_MODE_HS_ANY),
    - PHY_TRSV_REG_CFG(0x03c, 0x7f, PWR_MODE_HS_ANY),
    - PHY_TRSV_REG_CFG(0x048, 0xc0, PWR_MODE_HS_ANY),
    + PHY_TRSV_REG_CFG_AUTOV9(0x032, 0xbc, PWR_MODE_HS_ANY),
    + PHY_TRSV_REG_CFG_AUTOV9(0x03c, 0x7f, PWR_MODE_HS_ANY),
    + PHY_TRSV_REG_CFG_AUTOV9(0x048, 0xc0, PWR_MODE_HS_ANY),

    - PHY_TRSV_REG_CFG(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
    - PHY_TRSV_REG_CFG(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
    - PWR_MODE_HS_G3_SER_B),
    - PHY_TRSV_REG_CFG(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),
    + PHY_TRSV_REG_CFG_AUTOV9(0x04a, 0x00, PWR_MODE_HS_G3_SER_B),
    + PHY_TRSV_REG_CFG_AUTOV9(0x04b, 0x10, PWR_MODE_HS_G1_SER_B |
    + PWR_MODE_HS_G3_SER_B),
    + PHY_TRSV_REG_CFG_AUTOV9(0x04d, 0x63, PWR_MODE_HS_G3_SER_B),

    END_UFS_PHY_CFG,
    };
    --
    2.35.1


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