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    Subject[PATCH 5.15 205/779] arm64: tegra: Mark BPMP channels as no-memory-wc
    Date
    From: Mikko Perttunen <mperttunen@nvidia.com>

    [ Upstream commit 61192a9d8a6367ae1b8234876941b037910a2459 ]

    The Tegra SYSRAM contains regions access to which is restricted to
    certain hardware blocks on the system, and speculative accesses to
    those will cause issues.

    Patch 'misc: sram: Only map reserved areas in Tegra SYSRAM' attempted
    to resolve this by only mapping the regions specified in the device
    tree on the assumption that there are no such restricted areas within
    the 64K-aligned area of memory that contains the memory we wish to map.

    Turns out this assumption is wrong, as there are such areas above the
    4K pages described in the device trees. As such, we need to use the
    bigger hammer that is no-memory-wc, which causes the memory to be
    mapped as Device memory to which speculative accesses are disallowed.

    As such, the previous patch in the series,
    'firmware: tegra: bpmp: do only aligned access to IPC memory area',
    is required with this patch to make the BPMP driver only issue aligned
    memory accesses as those are also required with Device memory.

    Fixes: fec29bf04994 ("misc: sram: Only map reserved areas in Tegra SYSRAM")
    Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
    Reviewed-by: Yousaf Kaukab <ykaukab@suse.de>
    Signed-off-by: Thierry Reding <treding@nvidia.com>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
    arch/arm64/boot/dts/nvidia/tegra194.dtsi | 1 +
    arch/arm64/boot/dts/nvidia/tegra234.dtsi | 1 +
    3 files changed, 3 insertions(+)

    diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
    index 8354512d7b1c..5b0bc9aa1a42 100644
    --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
    +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
    @@ -1583,6 +1583,7 @@ sram@30000000 {
    #address-cells = <1>;
    #size-cells = <1>;
    ranges = <0x0 0x0 0x30000000 0x50000>;
    + no-memory-wc;

    cpu_bpmp_tx: sram@4e000 {
    reg = <0x4e000 0x1000>;
    diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
    index a56fb83839a4..ca71b71d801a 100644
    --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
    +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
    @@ -2249,6 +2249,7 @@ sram@40000000 {
    #address-cells = <1>;
    #size-cells = <1>;
    ranges = <0x0 0x0 0x40000000 0x50000>;
    + no-memory-wc;

    cpu_bpmp_tx: sram@4e000 {
    reg = <0x4e000 0x1000>;
    diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
    index 144a7eb699a7..2b4784572220 100644
    --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
    +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
    @@ -128,6 +128,7 @@ sram@40000000 {
    #address-cells = <1>;
    #size-cells = <1>;
    ranges = <0x0 0x0 0x40000000 0x80000>;
    + no-memory-wc;

    cpu_bpmp_tx: sram@70000 {
    reg = <0x70000 0x1000>;
    --
    2.35.1


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