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    Subject[PATCH 3/3] arm64: dts: qcom: sm6350: Add GPI DMA nodes
    Date
    Add nodes for the gpi_dma0 and gpi_dma1 which are (optionally) used for
    various i2c busses based on the qup firmware configuration.

    Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
    ---
    arch/arm64/boot/dts/qcom/sm6350.dtsi | 59 ++++++++++++++++++++++++++++
    1 file changed, 59 insertions(+)

    diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
    index 76f14d54ae1c..5de6eb26f904 100644
    --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
    @@ -5,6 +5,7 @@

    #include <dt-bindings/clock/qcom,gcc-sm6350.h>
    #include <dt-bindings/clock/qcom,rpmh.h>
    +#include <dt-bindings/dma/qcom-gpi.h>
    #include <dt-bindings/gpio/gpio.h>
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/mailbox/qcom-ipcc.h>
    @@ -517,6 +518,26 @@ opp-384000000 {
    };
    };

    + gpi_dma0: dma-controller@800000 {
    + compatible = "qcom,sm6350-gpi-dma";
    + reg = <0 0x00800000 0 0x60000>;
    + interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
    + dma-channels = <10>;
    + dma-channel-mask = <0x1f>;
    + iommus = <&apps_smmu 0x56 0x0>;
    + #dma-cells = <3>;
    + status = "disabled";
    + };
    +
    qupv3_id_0: geniqup@8c0000 {
    compatible = "qcom,geni-se-qup";
    reg = <0x0 0x8c0000 0x0 0x2000>;
    @@ -537,6 +558,9 @@ i2c0: i2c@880000 {
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c0_default>;
    interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
    + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
    + <&gpi_dma0 1 0 QCOM_GPI_I2C>;
    + dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
    @@ -550,12 +574,35 @@ i2c2: i2c@888000 {
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c2_default>;
    interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
    + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
    + <&gpi_dma0 1 2 QCOM_GPI_I2C>;
    + dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
    };
    };

    + gpi_dma1: dma-controller@900000 {
    + compatible = "qcom,sm6350-gpi-dma";
    + reg = <0 0x00900000 0 0x60000>;
    + interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 648 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 650 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 653 IRQ_TYPE_LEVEL_HIGH>,
    + <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH>;
    + dma-channels = <10>;
    + dma-channel-mask = <0x3f>;
    + iommus = <&apps_smmu 0x4d6 0x0>;
    + #dma-cells = <3>;
    + status = "disabled";
    + };
    +
    qupv3_id_1: geniqup@9c0000 {
    compatible = "qcom,geni-se-qup";
    reg = <0x0 0x9c0000 0x0 0x2000>;
    @@ -576,6 +623,9 @@ i2c6: i2c@980000 {
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c6_default>;
    interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
    + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
    + <&gpi_dma1 1 0 QCOM_GPI_I2C>;
    + dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
    @@ -589,6 +639,9 @@ i2c7: i2c@984000 {
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c7_default>;
    interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
    + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
    + <&gpi_dma1 1 1 QCOM_GPI_I2C>;
    + dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
    @@ -602,6 +655,9 @@ i2c8: i2c@988000 {
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c8_default>;
    interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
    + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
    + <&gpi_dma1 1 2 QCOM_GPI_I2C>;
    + dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
    @@ -626,6 +682,9 @@ i2c10: i2c@990000 {
    pinctrl-names = "default";
    pinctrl-0 = <&qup_i2c10_default>;
    interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
    + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
    + <&gpi_dma1 1 4 QCOM_GPI_I2C>;
    + dma-names = "tx", "rx";
    #address-cells = <1>;
    #size-cells = <0>;
    status = "disabled";
    --
    2.37.1
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