Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Thu, 11 Aug 2022 16:47:50 +0200 | Subject | Re: [PATCH v3 3/3] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} |
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On Fri, Jul 22, 2022 at 5:12 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 > and ETH1 respectively. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v2->v3 > * Included irqc-rzg2l.h header
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v6.1.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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