Messages in this thread Patch in this message | | | From | Conor Dooley <> | Subject | [PATCH 4/4] dt-bindings: PCI: microchip,pcie-host: fix missing address translation property | Date | Thu, 11 Aug 2022 21:33:07 +0100 |
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From: Conor Dooley <conor.dooley@microchip.com>
When the PCI controller node was added to the PolarFire SoC dtsi, dt-schema was not able to detect the presence of some undocumented properties due to how it handled unevaluatedProperties. v2022.08 introduces better validation, producing the following error:
arch/riscv/boot/dts/microchip/mpfs-polarberry.dtb: pcie@2000000000: Unevaluated properties are not allowed ('clock-names', 'microchip,axi-m-atr0' were unexpected) From schema: Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
Fixes: 528a5b1f2556 ("riscv: dts: microchip: add new peripherals to icicle kit device tree") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- I feel like there's a pretty good chance that this is not the way this should have been done and the property should be marked as deprecated but I don't know enough about PCI to answer that. --- .../devicetree/bindings/pci/microchip,pcie-host.yaml | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 9b123bcd034c..9ac34b33c4b2 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -71,6 +71,17 @@ properties: msi-parent: description: MSI controller the device is capable of using. + microchip,axi-m-atr0: + description: | + Depending on the FPGA bitstream, the AXIM address translation table in the + PCIe controllers bridge layer may need to be configured. Use this property + to set the address offset. For more information, see Section 1.3.3, + "PCIe/AXI4 Address Translation" of the PolarFire SoC PCIe User Guide: + https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 2 + maxItems: 2 + legacy-interrupt-controller: type: object properties: -- 2.37.1
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