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Subject[PATCH v1] PCI/PM: Switch D3Hot delay to use usleep_range
From: Sajid Dalvi <>

Since the PCI spec requires a 10ms D3Hot delay (defined by
PCI_PM_D3HOT_WAIT) and a few of the PCI quirks update the D3Hot delay up
to 20ms, let's switch from msleep to usleep_range to improve the delay

This patch came from Sajid Dalvi <> in the Pixel 6
kernel tree [1]. Testing on a Pixel 6, found that the 10ms delay for
the Exynos PCIe device was on average delaying for 19ms when the spec
requires 10ms. Switching from msleep to uslseep_delay therefore
decreases the resume time on a Pixel 6 on average by 9ms.


Signed-off-by: Sajid Dalvi <>
Signed-off-by: Will McVicker <>
drivers/pci/pci.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 95bc329e74c0..5ae5b3c4dc9b 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -72,7 +72,8 @@ static void pci_dev_d3_sleep(struct pci_dev *dev)
delay = pci_pm_d3hot_delay;

if (delay)
- msleep(delay);
+ usleep_range(delay * USEC_PER_MSEC,
+ (delay + 2) * USEC_PER_MSEC);

bool pci_reset_supported(struct pci_dev *dev)
base-commit: 2ae08b36c06ea8df73a79f6b80ff7964e006e9e3

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