Messages in this thread | | | Date | Fri, 8 Jul 2022 10:13:29 +0200 | Subject | Re: [RESEND v4 2/2] i2c: mediatek: Add i2c compatible for Mediatek MT8188 | From | AngeloGioacchino Del Regno <> |
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Il 08/07/22 05:47, kewei.xu@mediatek.com ha scritto: > From: Kewei Xu <kewei.xu@mediatek.com> > > Add i2c compatible for MT8188. Compare to MT8192 i2c controller, > The MT8188 i2c OFFSET_SLAVE_ADDR register changed from 0x04 to 0x94. > > Signed-off-by: Kewei Xu <kewei.xu@mediatek.com> > --- > v4: no changes > V3: no changes > V2: added mt_i2c_regs_v3[] to replace slave_addr_version. > --- > drivers/i2c/busses/i2c-mt65xx.c | 43 +++++++++++++++++++++++++++++++++ > 1 file changed, 43 insertions(+) > > diff --git a/drivers/i2c/busses/i2c-mt65xx.c b/drivers/i2c/busses/i2c-mt65xx.c > index 8e6985354fd5..70aff42adf5d 100644 > --- a/drivers/i2c/busses/i2c-mt65xx.c > +++ b/drivers/i2c/busses/i2c-mt65xx.c > @@ -229,6 +229,35 @@ static const u16 mt_i2c_regs_v2[] = { > [OFFSET_DCM_EN] = 0xf88, > }; > > +static const u16 mt_i2c_regs_v3[] = { > + [OFFSET_DATA_PORT] = 0x0,
> + [OFFSET_SLAVE_ADDR] = 0x94,
Please keep this list ordered by register offset.
> + [OFFSET_INTR_MASK] = 0x8, > + [OFFSET_INTR_STAT] = 0xc, > + [OFFSET_CONTROL] = 0x10, > + [OFFSET_TRANSFER_LEN] = 0x14, > + [OFFSET_TRANSAC_LEN] = 0x18, > + [OFFSET_DELAY_LEN] = 0x1c, > + [OFFSET_TIMING] = 0x20, > + [OFFSET_START] = 0x24, > + [OFFSET_EXT_CONF] = 0x28, > + [OFFSET_LTIMING] = 0x2c, > + [OFFSET_HS] = 0x30, > + [OFFSET_IO_CONFIG] = 0x34, > + [OFFSET_FIFO_ADDR_CLR] = 0x38, > + [OFFSET_SDA_TIMING] = 0x3c, > + [OFFSET_TRANSFER_LEN_AUX] = 0x44, > + [OFFSET_CLOCK_DIV] = 0x48, > + [OFFSET_SOFTRESET] = 0x50, > + [OFFSET_MULTI_DMA] = 0x8c, > + [OFFSET_SCL_MIS_COMP_POINT] = 0x90,
[OFFSET_SLAVE_ADDR] = 0x94 goes here,
after which:
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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