Messages in this thread | | | Date | Thu, 7 Jul 2022 10:12:01 +0200 | Subject | Re: [PATCH 1/3] drm/bridge: fsl-ldb: Fix mode clock rate validation | From | Neil Armstrong <> |
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Hi,
On 06/07/2022 15:34, Robert Foss wrote: > On Fri, 1 Jul 2022 at 13:00, Marek Vasut <marex@denx.de> wrote: >> >> On 7/1/22 08:56, Liu Ying wrote: >>> With LVDS dual link, up to 160MHz mode clock rate is supported. >>> With LVDS single link, up to 80MHz mode clock rate is supported. >>> Fix mode clock rate validation by swapping the maximum mode clock >>> rates of the two link modes. >>> >>> Fixes: 463db5c2ed4a ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB bridge") >>> Cc: Andrzej Hajda <andrzej.hajda@intel.com> >>> Cc: Neil Armstrong <narmstrong@baylibre.com> >>> Cc: Robert Foss <robert.foss@linaro.org> >>> Cc: Laurent Pinchart <Laurent.pinchart@ideasonboard.com> >>> Cc: Jonas Karlman <jonas@kwiboo.se> >>> Cc: Jernej Skrabec <jernej.skrabec@gmail.com> >>> Cc: David Airlie <airlied@linux.ie> >>> Cc: Daniel Vetter <daniel@ffwll.ch> >>> Cc: Sam Ravnborg <sam@ravnborg.org> >>> Cc: Marek Vasut <marex@denx.de> >>> Cc: NXP Linux Team <linux-imx@nxp.com> >>> Signed-off-by: Liu Ying <victor.liu@nxp.com> >> >> Reviewed-by: Marek Vasut <marex@denx.de> > > Applied 1-2/3 to drm-misc-next. Picked Mareks patch for 3/3 since it > was submitted first and is identical.
Seems we'll have a conflict when drm-misc-fixes is backmerged in drm-misc-next !
Neil
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