lkml.org 
[lkml]   [2022]   [Jul]   [5]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
From
Date
SubjectRe: [PATCH v6 2/4] dt-bindings: riscv: document cbom-block-size
Reviewed-by: Guo Ren <guoren@kernel.org>

On Wed, Jul 6, 2022 at 6:47 AM Heiko Stuebner <heiko@sntech.de> wrote:
>
> The Zicbom operates on a block-size defined for the cpu-core,
> which does not necessarily match other cache-sizes used.
>
> So add the necessary property for the system to know the core's
> block-size.
>
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> Reviewed-by: Anup Patel <anup@brainfault.org>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index d632ac76532e..873dd12f6e89 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -63,6 +63,11 @@ properties:
> - riscv,sv48
> - riscv,none
>
> + riscv,cbom-block-size:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + The blocksize in bytes for the Zicbom cache operations.
> +
> riscv,isa:
> description:
> Identifies the specific RISC-V instruction set architecture
> --
> 2.35.1
>


--
Best Regards
Guo Ren

\
 
 \ /
  Last update: 2022-07-06 01:58    [W:0.060 / U:0.620 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site