lkml.org 
[lkml]   [2022]   [Jul]   [5]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
/
Date
SubjectRe: [PATCH 01/14] arm64: dts: qcom: sc7280: drop PCIe PHY clock index
From
On 05/07/2022 14:40, Johan Hovold wrote:
> The QMP PCIe PHY provides a single clock so drop the redundant clock
> index.
>
> Signed-off-by: Johan Hovold <johan+linaro@kernel.org>

Hmm. After checking the source code, the clocks entry of the phy@1c0e000
node also needs to be fixed.

And also maybe:

Fixes: bd7d507935ca ("arm64: dts: qcom: sc7280: Add pcie clock support")
Fixes: 92e0ee9f83b3 ("arm64: dts: qcom: sc7280: Add PCIe and PHY related
nodes")


> ---
> arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index e66fc67de206..b0ae2dbba50f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -818,7 +818,7 @@ gcc: clock-controller@100000 {
> reg = <0 0x00100000 0 0x1f0000>;
> clocks = <&rpmhcc RPMH_CXO_CLK>,
> <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>,
> - <0>, <&pcie1_lane 0>,
> + <0>, <&pcie1_lane>,
> <0>, <0>, <0>, <0>;
> clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
> "pcie_0_pipe_clk", "pcie_1_pipe_clk",
> @@ -2110,7 +2110,7 @@ pcie1_lane: phy@1c0e200 {
> clock-names = "pipe0";
>
> #phy-cells = <0>;
> - #clock-cells = <1>;
> + #clock-cells = <0>;
> clock-output-names = "pcie_1_pipe_clk";
> };
> };


--
With best wishes
Dmitry

\
 
 \ /
  Last update: 2022-07-05 15:22    [W:0.144 / U:0.504 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site