Messages in this thread | | | Date | Mon, 4 Jul 2022 16:20:08 +0100 | From | Sudeep Holla <> | Subject | Re: [PATCH v6 00/21] arch_topology: Updates to add socket support and fix cluster ids |
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On Mon, Jul 04, 2022 at 03:10:30PM +0000, Conor.Dooley@microchip.com wrote: > On 04/07/2022 11:15, Sudeep Holla wrote: > > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe > > > > Hi Greg, > > > > Let me know if you prefer to pull the patches directly or prefer pull > > request. It has been in -next for a while now. > > > > Hi All, > > > > This version updates cacheinfo to populate and use the information from > > there for all the cache topology. > > > > This series intends to fix some discrepancies we have in the CPU topology > > parsing from the device tree /cpu-map node. Also this diverges from the > > behaviour on a ACPI enabled platform. The expectation is that both DT > > and ACPI enabled systems must present consistent view of the CPU topology. > > > > Currently we assign generated cluster count as the physical package identifier > > for each CPU which is wrong. The device tree bindings for CPU topology supports > > sockets to infer the socket or physical package identifier for a given CPU. > > Also we don't check if all the cores/threads belong to the same cluster before > > updating their sibling masks which is fine as we don't set the cluster id yet. > > > > These changes also assigns the cluster identifier as parsed from the device tree > > cluster nodes within /cpu-map without support for nesting of the clusters. > > Finally, it also add support for socket nodes in /cpu-map. With this the > > parsing of exact same information from ACPI PPTT and /cpu-map DT node > > aligns well. > > > > The only exception is that the last level cache id information can be > > inferred from the same ACPI PPTT while we need to parse CPU cache nodes > > in the device tree. > > For DT + RISC-V on PolarFire SoC and SiFive fu540 > Tested-by: Conor Dooley <conor.dooley@microchip.com> > > Anecdotally, v5 was tested on the !SMP D1 which worked fine when > CONFIG_SMP was enabled. >
Thanks a lot for testing on RISC-V, much appreciated! Thanks for your patience and help with v5 so that we could figure out the silly issue finally.
-- Regards, Sudeep
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