lkml.org 
[lkml]   [2022]   [Jul]   [3]   [last100]   RSS Feed
Views: [wrap][no wrap]   [headers]  [forward] 
 
Messages in this thread
Patch in this message
/
From
Subject[PATCH 7/9] ARM: dts: uniphier: Add ahci controller and glue layer nodes for PXs2
Date
Add ahci controller and glue layer nodes including reset and phy.
This supports for PXs2 and the boards without PXs2 vodka board that
doesn't implement any SATA connectors.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm/boot/dts/uniphier-pxs2-gentil.dts | 4 +++
arch/arm/boot/dts/uniphier-pxs2.dtsi | 40 ++++++++++++++++++++++
2 files changed, 44 insertions(+)

diff --git a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
index 759384b60663..5f18b926c50a 100644
--- a/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
+++ b/arch/arm/boot/dts/uniphier-pxs2-gentil.dts
@@ -99,3 +99,7 @@ &usb0 {
&usb1 {
status = "okay";
};
+
+&ahci {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index 7d8c437b8f8b..04e9467734c4 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -599,6 +599,46 @@ mdio: mdio {
};
};

+ ahci: ahci@65600000 {
+ compatible = "socionext,uniphier-pxs2-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65600000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 28>;
+ resets = <&sys_rst 28>, <&ahci_rst 0>;
+ ports-implemented = <1>;
+ phys = <&ahci_phy>;
+ };
+
+ ahci-glue@65700000 {
+ compatible = "socionext,uniphier-pxs2-ahci-glue",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65700000 0x100>;
+
+ ahci_rst: reset@0 {
+ compatible = "socionext,uniphier-pxs2-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "link";
+ clocks = <&sys_clk 28>;
+ reset-names = "link";
+ resets = <&sys_rst 28>;
+ #reset-cells = <1>;
+ };
+
+ ahci_phy: phy@10 {
+ compatible = "socionext,uniphier-pxs2-ahci-phy";
+ reg = <0x10 0x10>;
+ clock-names = "link";
+ clocks = <&sys_clk 28>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 28>, <&sys_rst 30>;
+ #phy-cells = <0>;
+ };
+ };
+
usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
--
2.25.1
\
 
 \ /
  Last update: 2022-07-04 02:22    [W:0.359 / U:0.288 seconds]
©2003-2020 Jasper Spaans|hosted at Digital Ocean and TransIP|Read the blog|Advertise on this site