Messages in this thread | | | Date | Mon, 25 Jul 2022 11:46:32 +0200 | Subject | Re: [PATCH] KVM: SVM: Do not virtualize MSR accesses for APIC LVTT register | From | Paolo Bonzini <> |
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On 7/25/22 05:34, Suravee Suthikulpanit wrote: > AMD does not support APIC TSC-deadline timer mode. AVIC hardware > will generate GP fault when guest kernel writes 1 to bits [18] > of the APIC LVTT register (offset 0x32) to set the timer mode. > (Note: bit 18 is reserved on AMD system). > > Therefore, always intercept and let KVM emulate the MSR accesses. > > Fixes: f3d7c8aa6882 ("KVM: SVM: Fix x2APIC MSRs interception") > Signed-off-by: Suravee Suthikulpanit<suravee.suthikulpanit@amd.com>
Does this fix some kvm-unit-tests testcase?
Anyway, I queued the patch, thanks!
Paolo
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