Messages in this thread | | | Date | Tue, 26 Jul 2022 10:55:50 +0800 | Subject | Re: [PATCH 1/2] scsi: ufs: Add Multi-Circular Queue support | From | Can Guo <> |
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Hi Avri,
On 7/23/2022 10:59 PM, Avri Altman wrote: >> +#define MCQ_ROP_OFFSET_n(p, i) \ >> + hba->mcq_rop[(p)].offset + hba->mcq_rop[(p)].stride * (i) > Can you please explain the 0x100 stride thing? > Theoretically, each rop set is 48Bytes long, or did I get it wrong?
In the draft, there are 4 sets of MCQ Operation & Runtime Registers, i.e. SQD_n, SQIS_n, CQD_n and CQIS_n.
They may be interleaved or segregated, depends on realistic HW designs.
For example, either #1 or #2 can be the case, and QCOM uses case #1, in which 'stride' means the size (in bytes)
that one register has to hop over to reach the same register on next round (for example, addr of SQHP_n == (addr of SQHP_0) + (stride * n)).
To allow flexibility, SoC vendors, depends on realistic HW designs, (by using vops_config_mcq_rop) can manipulate
the 'offset' and 'stride' of each MCQ Operation & Runtime Register such that SQDAO_n, SQISAO_n, CQDAO_n and
CQISAO_n are programmed with wanted offsets/values.
#1 -
SQHP_0 SQTP_0 SQRTC_0 SQCTI_0 SQRTS_0 SQIS_0 SQIE_0 CQHP_0 CQTP_0 CQIS_0 CQIE_0 CQIACR_0 SQHP_1 SQTP_1 SQRTC_1 SQCTI_1 SQRTS_1 SQIS_1 SQIE_1 CQHP_1 CQTP_1 CQIS_1 CQIE_1 CQIACR_1 ... SQHP_n SQTP_n SQRTC_n SQCTI_n SQRTS_n SQIS_n SQIE_n CQHP_n CQTP_n CQIS_n CQIE_n CQIACR_n
#2 -
SQHP_0 SQTP_0 SQRTC_0 SQCTI_0 SQRTS_0 SQHP_1 SQTP_1 SQRTC_1 SQCTI_1 SQRTS_1 ... SQHP_n SQTP_n SQRTC_n SQCTI_n SQRTS_n
SQIS_0 SQIE_0 SQIS_1 SQIE_1 ... SQIS_n SQIE_n
CQHP_0 CQTP_0 CQHP_1 CQTP_1 ... CQHP_n CQTP_n
CQIS_0 CQIE_0 CQIACR_0 CQIS_1 CQIE_1 CQIACR_1 ... CQIS_n CQIE_n CQIACR_n
Thanks,
Can Guo.
> Thanks, > Avri
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