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    Subject[PATCH 5.18 45/70] x86/speculation: Remove x86_spec_ctrl_mask
    Date
    From: Josh Poimboeuf <jpoimboe@kernel.org>

    commit acac5e98ef8d638a411cfa2ee676c87e1973f126 upstream.

    This mask has been made redundant by kvm_spec_ctrl_test_value(). And it
    doesn't even work when MSR interception is disabled, as the guest can
    just write to SPEC_CTRL directly.

    Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/x86/kernel/cpu/bugs.c | 31 +------------------------------
    1 file changed, 1 insertion(+), 30 deletions(-)

    --- a/arch/x86/kernel/cpu/bugs.c
    +++ b/arch/x86/kernel/cpu/bugs.c
    @@ -86,12 +86,6 @@ u64 spec_ctrl_current(void)
    EXPORT_SYMBOL_GPL(spec_ctrl_current);

    /*
    - * The vendor and possibly platform specific bits which can be modified in
    - * x86_spec_ctrl_base.
    - */
    -static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS;
    -
    -/*
    * AMD specific MSR info for Speculative Store Bypass control.
    * x86_amd_ls_cfg_ssbd_mask is initialized in identify_boot_cpu().
    */
    @@ -146,10 +140,6 @@ void __init check_bugs(void)
    if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
    rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);

    - /* Allow STIBP in MSR_SPEC_CTRL if supported */
    - if (boot_cpu_has(X86_FEATURE_STIBP))
    - x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
    -
    /* Select the proper CPU mitigations before patching alternatives: */
    spectre_v1_select_mitigation();
    spectre_v2_select_mitigation();
    @@ -208,19 +198,10 @@ void __init check_bugs(void)
    void
    x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
    {
    - u64 msrval, guestval, hostval = spec_ctrl_current();
    + u64 msrval, guestval = guest_spec_ctrl, hostval = spec_ctrl_current();
    struct thread_info *ti = current_thread_info();

    - /* Is MSR_SPEC_CTRL implemented ? */
    if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
    - /*
    - * Restrict guest_spec_ctrl to supported values. Clear the
    - * modifiable bits in the host base value and or the
    - * modifiable bits from the guest value.
    - */
    - guestval = hostval & ~x86_spec_ctrl_mask;
    - guestval |= guest_spec_ctrl & x86_spec_ctrl_mask;
    -
    if (hostval != guestval) {
    msrval = setguest ? guestval : hostval;
    wrmsrl(MSR_IA32_SPEC_CTRL, msrval);
    @@ -1659,16 +1640,6 @@ static enum ssb_mitigation __init __ssb_
    }

    /*
    - * If SSBD is controlled by the SPEC_CTRL MSR, then set the proper
    - * bit in the mask to allow guests to use the mitigation even in the
    - * case where the host does not enable it.
    - */
    - if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
    - static_cpu_has(X86_FEATURE_AMD_SSBD)) {
    - x86_spec_ctrl_mask |= SPEC_CTRL_SSBD;
    - }
    -
    - /*
    * We have three CPU feature flags that are in play here:
    * - X86_BUG_SPEC_STORE_BYPASS - CPU is susceptible.
    * - X86_FEATURE_SSBD - CPU is able to turn off speculative store bypass

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