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    Subject[PATCH v1 15/31] perf vendor events: Update Intel ivybridge
    From
    Use script at:
    https://github.com/intel/event-converter-for-linux-perf/blob/master/download_and_gen.py

    to download and generate the latest events and metrics. Manually copy
    the ivybridge files into perf and update mapfile.csv.

    Tested on a non-ivybridge with 'perf test':
    10: PMU events :
    10.1: PMU event table sanity : Ok
    10.2: PMU event map aliases : Ok
    10.3: Parsing of PMU event table metrics : Ok
    10.4: Parsing of PMU event table metrics with fake PMUs : Ok

    Signed-off-by: Ian Rogers <irogers@google.com>
    ---
    .../pmu-events/arch/x86/ivybridge/cache.json | 2 +-
    .../arch/x86/ivybridge/floating-point.json | 2 +-
    .../arch/x86/ivybridge/frontend.json | 2 +-
    .../arch/x86/ivybridge/ivb-metrics.json | 94 +++++++++++++------
    .../pmu-events/arch/x86/ivybridge/memory.json | 2 +-
    .../pmu-events/arch/x86/ivybridge/other.json | 2 +-
    .../arch/x86/ivybridge/pipeline.json | 4 +-
    .../arch/x86/ivybridge/uncore-other.json | 2 +-
    .../arch/x86/ivybridge/virtual-memory.json | 2 +-
    tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
    10 files changed, 75 insertions(+), 39 deletions(-)

    diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
    index 62e9705daa19..8adb2e45e23d 100644
    --- a/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
    +++ b/tools/perf/pmu-events/arch/x86/ivybridge/cache.json
    @@ -1099,4 +1099,4 @@
    "SampleAfterValue": "100003",
    "UMask": "0x10"
    }
    -]
    \ No newline at end of file
    +]
    diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json
    index db8b1c4fceb0..4c2ac010cf55 100644
    --- a/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json
    +++ b/tools/perf/pmu-events/arch/x86/ivybridge/floating-point.json
    @@ -166,4 +166,4 @@
    "SampleAfterValue": "2000003",
    "UMask": "0x1"
    }
    -]
    \ No newline at end of file
    +]
    diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
    index c956a0a51312..2b1a82dd86ab 100644
    --- a/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
    +++ b/tools/perf/pmu-events/arch/x86/ivybridge/frontend.json
    @@ -312,4 +312,4 @@
    "SampleAfterValue": "2000003",
    "UMask": "0x1"
    }
    -]
    \ No newline at end of file
    +]
    diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
    index 87670226f52d..3f48e75f8a86 100644
    --- a/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
    +++ b/tools/perf/pmu-events/arch/x86/ivybridge/ivb-metrics.json
    @@ -130,17 +130,11 @@
    "MetricName": "FLOPc_SMT"
    },
    {
    - "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
    + "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is execution) per-core",
    "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
    "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
    "MetricName": "ILP"
    },
    - {
    - "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
    - "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
    - "MetricGroup": "Bad;BadSpec;BrMispredicts",
    - "MetricName": "IpMispredict"
    - },
    {
    "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
    "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
    @@ -196,6 +190,18 @@
    "MetricGroup": "Summary;TmaL1",
    "MetricName": "Instructions"
    },
    + {
    + "BriefDescription": "Average number of Uops retired in cycles where at least one uop has retired.",
    + "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / cpu@UOPS_RETIRED.RETIRE_SLOTS\\,cmask\\=1@",
    + "MetricGroup": "Pipeline;Ret",
    + "MetricName": "Retire"
    + },
    + {
    + "BriefDescription": "",
    + "MetricExpr": "UOPS_EXECUTED.THREAD / cpu@UOPS_EXECUTED.THREAD\\,cmask\\=1@",
    + "MetricGroup": "Cor;Pipeline;PortsUtil;SMT",
    + "MetricName": "Execute"
    + },
    {
    "BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
    "MetricExpr": "IDQ.DSB_UOPS / (( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS ) )",
    @@ -203,11 +209,16 @@
    "MetricName": "DSB_Coverage"
    },
    {
    - "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)",
    + "BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear) (lower number means higher occurrence rate)",
    + "MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
    + "MetricGroup": "Bad;BadSpec;BrMispredicts",
    + "MetricName": "IpMispredict"
    + },
    + {
    + "BriefDescription": "Actual Average Latency for L1 data-cache miss demand load operations (in core cycles)",
    "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
    "MetricGroup": "Mem;MemoryBound;MemoryLat",
    - "MetricName": "Load_Miss_Real_Latency",
    - "PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings."
    + "MetricName": "Load_Miss_Real_Latency"
    },
    {
    "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
    @@ -215,24 +226,6 @@
    "MetricGroup": "Mem;MemoryBound;MemoryBW",
    "MetricName": "MLP"
    },
    - {
    - "BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
    - "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
    - "MetricGroup": "Mem;MemoryBW",
    - "MetricName": "L1D_Cache_Fill_BW"
    - },
    - {
    - "BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
    - "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
    - "MetricGroup": "Mem;MemoryBW",
    - "MetricName": "L2_Cache_Fill_BW"
    - },
    - {
    - "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
    - "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
    - "MetricGroup": "Mem;MemoryBW",
    - "MetricName": "L3_Cache_Fill_BW"
    - },
    {
    "BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
    "MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
    @@ -264,6 +257,48 @@
    "MetricGroup": "Mem;MemoryTLB_SMT",
    "MetricName": "Page_Walks_Utilization_SMT"
    },
    + {
    + "BriefDescription": "Average per-core data fill bandwidth to the L1 data cache [GB / sec]",
    + "MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
    + "MetricGroup": "Mem;MemoryBW",
    + "MetricName": "L1D_Cache_Fill_BW"
    + },
    + {
    + "BriefDescription": "Average per-core data fill bandwidth to the L2 cache [GB / sec]",
    + "MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
    + "MetricGroup": "Mem;MemoryBW",
    + "MetricName": "L2_Cache_Fill_BW"
    + },
    + {
    + "BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
    + "MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
    + "MetricGroup": "Mem;MemoryBW",
    + "MetricName": "L3_Cache_Fill_BW"
    + },
    + {
    + "BriefDescription": "Average per-thread data fill bandwidth to the L1 data cache [GB / sec]",
    + "MetricExpr": "(64 * L1D.REPLACEMENT / 1000000000 / duration_time)",
    + "MetricGroup": "Mem;MemoryBW",
    + "MetricName": "L1D_Cache_Fill_BW_1T"
    + },
    + {
    + "BriefDescription": "Average per-thread data fill bandwidth to the L2 cache [GB / sec]",
    + "MetricExpr": "(64 * L2_LINES_IN.ALL / 1000000000 / duration_time)",
    + "MetricGroup": "Mem;MemoryBW",
    + "MetricName": "L2_Cache_Fill_BW_1T"
    + },
    + {
    + "BriefDescription": "Average per-thread data fill bandwidth to the L3 cache [GB / sec]",
    + "MetricExpr": "(64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time)",
    + "MetricGroup": "Mem;MemoryBW",
    + "MetricName": "L3_Cache_Fill_BW_1T"
    + },
    + {
    + "BriefDescription": "Average per-thread data access bandwidth to the L3 cache [GB / sec]",
    + "MetricExpr": "0",
    + "MetricGroup": "Mem;MemoryBW;Offcore",
    + "MetricName": "L3_Cache_Access_BW_1T"
    + },
    {
    "BriefDescription": "Average CPU Utilization",
    "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
    @@ -280,7 +315,8 @@
    "BriefDescription": "Giga Floating Point Operations Per Second",
    "MetricExpr": "( ( 1 * ( FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE + FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE ) + 2 * FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE + 4 * ( FP_COMP_OPS_EXE.SSE_PACKED_SINGLE + SIMD_FP_256.PACKED_DOUBLE ) + 8 * SIMD_FP_256.PACKED_SINGLE ) / 1000000000 ) / duration_time",
    "MetricGroup": "Cor;Flops;HPC",
    - "MetricName": "GFLOPs"
    + "MetricName": "GFLOPs",
    + "PublicDescription": "Giga Floating Point Operations Per Second. Aggregate across all supported options of: FP precisions, scalar and vector instructions, vector-width and AMX engine."
    },
    {
    "BriefDescription": "Average Frequency Utilization relative nominal frequency",
    diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json
    index 5f98f7746cf7..30fc0af61eb3 100644
    --- a/tools/perf/pmu-events/arch/x86/ivybridge/memory.json
    +++ b/tools/perf/pmu-events/arch/x86/ivybridge/memory.json
    @@ -233,4 +233,4 @@
    "SampleAfterValue": "100003",
    "UMask": "0x1"
    }
    -]
    \ No newline at end of file
    +]
    diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/other.json b/tools/perf/pmu-events/arch/x86/ivybridge/other.json
    index 83fe8f79adc6..2d62521791d8 100644
    --- a/tools/perf/pmu-events/arch/x86/ivybridge/other.json
    +++ b/tools/perf/pmu-events/arch/x86/ivybridge/other.json
    @@ -41,4 +41,4 @@
    "SampleAfterValue": "2000003",
    "UMask": "0x1"
    }
    -]
    \ No newline at end of file
    +]
    diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json
    index 2de31c56c2a5..d89d3f8db190 100644
    --- a/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json
    +++ b/tools/perf/pmu-events/arch/x86/ivybridge/pipeline.json
    @@ -676,7 +676,7 @@
    "UMask": "0x3"
    },
    {
    - "BriefDescription": "Number of occurences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
    + "BriefDescription": "Number of occurrences waiting for the checkpoints in Resource Allocation Table (RAT) to be recovered after Nuke due to all other cases except JEClear (e.g. whenever a ucode assist is needed like SSE exception, memory disambiguation, etc.)",
    "Counter": "0,1,2,3",
    "CounterHTOff": "0,1,2,3,4,5,6,7",
    "CounterMask": "1",
    @@ -1269,4 +1269,4 @@
    "SampleAfterValue": "2000003",
    "UMask": "0x1"
    }
    -]
    \ No newline at end of file
    +]
    diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json
    index 6278068908cf..88f1e326205f 100644
    --- a/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json
    +++ b/tools/perf/pmu-events/arch/x86/ivybridge/uncore-other.json
    @@ -82,10 +82,10 @@
    {
    "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
    "Counter": "Fixed",
    + "EventCode": "0xff",
    "EventName": "UNC_CLOCK.SOCKET",
    "PerPkg": "1",
    "PublicDescription": "This 48-bit fixed counter counts the UCLK cycles.",
    - "UMask": "0x01",
    "Unit": "ARB"
    }
    ]
    diff --git a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json
    index 8cf1549797b0..a5e387bbb134 100644
    --- a/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json
    +++ b/tools/perf/pmu-events/arch/x86/ivybridge/virtual-memory.json
    @@ -177,4 +177,4 @@
    "SampleAfterValue": "100007",
    "UMask": "0x20"
    }
    -]
    \ No newline at end of file
    +]
    diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
    index 727631ce1a57..cc34f6378d89 100644
    --- a/tools/perf/pmu-events/arch/x86/mapfile.csv
    +++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
    @@ -12,7 +12,7 @@ GenuineIntel-6-(3C|45|46),v31,haswell,core
    GenuineIntel-6-3F,v25,haswellx,core
    GenuineIntel-6-(7D|7E|A7),v1.14,icelake,core
    GenuineIntel-6-6[AC],v1.15,icelakex,core
    -GenuineIntel-6-3A,v18,ivybridge,core
    +GenuineIntel-6-3A,v22,ivybridge,core
    GenuineIntel-6-3E,v19,ivytown,core
    GenuineIntel-6-2D,v20,jaketown,core
    GenuineIntel-6-57,v9,knightslanding,core
    --
    2.37.1.359.gd136c6c3e2-goog
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