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SubjectRe: [PATCH v4 2/5] dt-bindings: phy: Add ARTPEC-8 PCIe phy
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On 20/07/2022 07:57, Wangseok Lee wrote:
> Add description to support Axis, ARTPEC-8 SoC. ARTPEC-8 is the SoC platform
> of Axis Communications and PCIe PHY is designed based on Samsung PHY.
>
> Signed-off-by: Wangseok Lee <wangseok.lee@samsung.com>
> ---
> v3->v4 :
> -Add "fsys-sysreg" to properties
> -Modify the "lcpll-ref-clk" and "clocks" in properties
> "lcpll-ref-clk" is custom properties, so add 'vendor', type(enum),
> description
> Add the maxItem in clocks, add clock-names in properties
>
> v2->v3 :
> -Modify version history to fit the linux commit rule
> -Remove 'Device Tree Bindings' on title
> -Remove clock-names entries
> -Change node name to soc from artpec8 on excamples
>
> v1->v2 :
> -'make dt_binding_check' result improvement
> -Add the missing property list
> -Align the indentation of continued lines/entries
> ---
> .../bindings/phy/axis,artpec8-pcie-phy.yaml | 85 ++++++++++++++++++++++
> 1 file changed, 85 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
> new file mode 100644
> index 0000000..9db39ef
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/axis,artpec8-pcie-phy.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/axis,artpec8-pcie-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: ARTPEC-8 SoC PCIe PHY
> +
> +maintainers:
> + - Jesper Nilsson <jesper.nilsson@axis.com>
> +
> +properties:
> + compatible:
> + const: axis,artpec8-pcie-phy
> +
> + reg:
> + items:
> + - description: PHY registers.
> + - description: PHY coding sublayer registers.
> +
> + reg-names:
> + items:
> + - const: phy
> + - const: pcs
> +
> + "#phy-cells":
> + const: 0
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: ref
> +
> + samsung,fsys-sysreg:
> + description:
> + Phandle to system register of fsys block.
> + $ref: /schemas/types.yaml#/definitions/phandle
> +
> + num-lanes:
> + const: 2
> +
> + axis,lcpll-ref-clk:
> + description:
> + select the reference clock of phy and initialization is performed
> + with the reference clock according to the selected value.
> + $ref: /schemas/types.yaml#/definitions/uint32

This looks like hardware register value... but after looking at driver
you rather need string... although REF_CLK_RESERVED is confusing. You
need to describe the feature, not some device programming model.

Then looking deeper it seems you just made a workaround around common
clock framework. At least for XO and SOC case - you just implemented a
clock mux in your PHY driver!

Implement a clock driver instead and handle only special case - clock
coming from IO.

Best regards,
Krzysztof

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