Messages in this thread Patch in this message | | | From | Anup Patel <> | Subject | [PATCH v7 5/7] RISC-V: Allow marking IPIs as suitable for remote FENCEs | Date | Wed, 20 Jul 2022 20:53:46 +0530 |
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To do remote FENCEs (i.e. remote TLB flushes) using IPI calls on the RISC-V kernel, we need hardware mechanism to directly inject IPI from the supervisor mode (i.e. RISC-V kernel) instead of using SBI calls.
The upcoming AIA IMSIC devices allow direct IPI injection from the supervisor mode (i.e. RISC-V kernel). To support this, we extend the riscv_ipi_set_virq_range() function so that IPI provider (i.e. irqchip drivers can mark IPIs as suitable for remote FENCEs.
Signed-off-by: Anup Patel <apatel@ventanamicro.com> --- arch/riscv/include/asm/smp.h | 19 +++++++++++++++++-- arch/riscv/kernel/sbi-ipi.c | 2 +- arch/riscv/kernel/smp.c | 12 +++++++++++- drivers/clocksource/timer-clint.c | 2 +- 4 files changed, 30 insertions(+), 5 deletions(-)
diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 7da034e2f231..f69fb9ac1756 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -16,6 +16,9 @@ struct seq_file; extern unsigned long boot_cpu_hartid; #ifdef CONFIG_SMP + +#include <linux/jump_label.h> + /* * Mapping between linux logical cpu index and hartid. */ @@ -46,7 +49,13 @@ void riscv_ipi_disable(void); bool riscv_ipi_have_virq_range(void); /* Set the IPI interrupt numbers for arch (called by irqchip drivers) */ -void riscv_ipi_set_virq_range(int virq, int nr_irqs, bool percpu_enable); +void riscv_ipi_set_virq_range(int virq, int nr_irqs, bool percpu_enable, + bool use_for_rfence); + +/* Check if we can use IPIs for remote FENCEs */ +DECLARE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +#define riscv_use_ipi_for_rfence() \ + static_branch_unlikely(&riscv_ipi_for_rfence) /* Secondary hart entry */ asmlinkage void smp_callin(void); @@ -94,10 +103,16 @@ static inline bool riscv_ipi_have_virq_range(void) } static inline void riscv_ipi_set_virq_range(int virq, int nr, - bool percpu_enable) + bool percpu_enable, + bool use_for_rfence) { } +static inline bool riscv_use_ipi_for_rfence(void) +{ + return false; +} + #endif /* CONFIG_SMP */ #if defined(CONFIG_HOTPLUG_CPU) && (CONFIG_SMP) diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c index 5be545f6914c..e45a7d9a16c2 100644 --- a/arch/riscv/kernel/sbi-ipi.c +++ b/arch/riscv/kernel/sbi-ipi.c @@ -55,6 +55,6 @@ void __init sbi_ipi_init(void) return; } - riscv_ipi_set_virq_range(virq, BITS_PER_LONG, false); + riscv_ipi_set_virq_range(virq, BITS_PER_LONG, false, false); pr_info("providing IPIs using SBI IPI extension\n"); } diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c index 07f1ff652362..80ab8359ad48 100644 --- a/arch/riscv/kernel/smp.c +++ b/arch/riscv/kernel/smp.c @@ -150,7 +150,11 @@ bool riscv_ipi_have_virq_range(void) return (ipi_virq_base) ? true : false; } -void riscv_ipi_set_virq_range(int virq, int nr, bool percpu_enable) +DEFINE_STATIC_KEY_FALSE(riscv_ipi_for_rfence); +EXPORT_SYMBOL_GPL(riscv_ipi_for_rfence); + +void riscv_ipi_set_virq_range(int virq, int nr, bool percpu_enable, + bool use_for_rfence) { int i, err; @@ -174,6 +178,12 @@ void riscv_ipi_set_virq_range(int virq, int nr, bool percpu_enable) /* Enabled IPIs for boot CPU immediately */ riscv_ipi_enable(); + + /* Update RFENCE static key */ + if (use_for_rfence) + static_branch_enable(&riscv_ipi_for_rfence); + else + static_branch_disable(&riscv_ipi_for_rfence); } EXPORT_SYMBOL_GPL(riscv_ipi_set_virq_range); diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 69f8d2ac1916..3a90b6b3ca48 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -245,7 +245,7 @@ static int __init clint_timer_init_dt(struct device_node *np) goto fail_remove_cpuhp; } - riscv_ipi_set_virq_range(virq, BITS_PER_LONG, false); + riscv_ipi_set_virq_range(virq, BITS_PER_LONG, false, true); clint_clear_ipi(clint_ipi_irq); return 0; -- 2.34.1
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