Messages in this thread | | | Subject | Re: [PATCH V18 00/13] irqchip: Add LoongArch-related irqchip drivers | From | Jianmin Lv <> | Date | Wed, 20 Jul 2022 20:06:10 +0800 |
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On 2022/7/20 下午7:03, Marc Zyngier wrote: > On Wed, 20 Jul 2022 11:51:19 +0100, > Jianmin Lv <lvjianmin@loongson.cn> wrote: >> >> LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. >> LoongArch includes a reduced 32-bit version (LA32R), a standard 32-bit >> version (LA32S) and a 64-bit version (LA64). LoongArch use ACPI as its >> boot protocol LoongArch-specific interrupt controllers (similar to APIC) >> are already added in the ACPI Specification 6.5(which may be published in >> early June this year and the board is reviewing the draft). >> >> Currently, LoongArch based processors (e.g. Loongson-3A5000) can only >> work together with LS7A chipsets. The irq chips in LoongArch computers >> include CPUINTC (CPU Core Interrupt Controller), LIOINTC (Legacy I/O >> Interrupt Controller), EIOINTC (Extended I/O Interrupt Controller), PCH-PIC >> (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller >> in LS7A chipset) and PCH-MSI (MSI Interrupt Controller). > > [...] > > OK, that's 4 versions in quick succession, so I suggest we stop the > bikeshedding and focus on getting this actually merged. > > I'm going to stick this in a branch and throw it at -next. Any change > will need to go on top of it, no rebasing. If anything that breaks > cannot be fixed easily, I will drop the branch. > > Thanks, > > M. >
Ok, Marc, thanks very much!
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