Messages in this thread | | | From | AngeloGioacchino Del Regno <> | Subject | [PATCH 0/2] MT8195: Add reset for T-PHY (usb/pcie) | Date | Wed, 20 Jul 2022 12:28:15 +0200 |
| |
Add the resets for TPHY Port 1 which, depending on the board layout, is used either as USB or PCIe PHY.
This is required on MT8195 Tomato Chromebooks for correct initialization of the secondary PCI-Express controller, where we have a MT7621 PCIe WiFi chip.
For reference, the PCIe1 controller devicetree node resets will look like this:
pcie@112f8000 { ... blurb ...
resets = <&infracfg_ao MT8195_INFRA_RST2_USBSIF_P1_SWRST>, <&infracfg_ao MT8195_INFRA_RST2_PCIE_P1_SWRST>; reset-names = "phy", "mac";
... blurb ... };
This series depends on an earlier one where I introduce the MAC resets for both PCIe (p0, p1) controllers [1]
[1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=654980
AngeloGioacchino Del Regno (2): dt-bindings: reset: mt8195: Add resets for USB/PCIe t-phy port 1 clk: mediatek: mt8195: Add reset idx for USB/PCIe T-PHY
drivers/clk/mediatek/clk-mt8195-infra_ao.c | 1 + include/dt-bindings/reset/mt8195-resets.h | 1 + 2 files changed, 2 insertions(+)
-- 2.35.1
| |